LP87702 datasheet(40/99 Pages) TI

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selection between signal use are set with the GPO1_SEL and GPO2_SEL bits in the GPO_CONTROL_2

The type of output, either push-pull (with V(VANA) level) or open drain, are set with the GPO0_OD and

GPO1_PG1_OD bits in the GPO_CONTROL_1 register and the GPO2_OD bit in the GPO_CONTROL_2

The logic level of the GPOx pins are is set by the GPO0_OUT and GPO1_OUT bits in the GPO_CONTROL_1

The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence

with ENx pin is selected by the GPOx_EN_PIN_CTRL bits. The delays during start-up and shutdown are set by

bits in the GPOx_DELAY registers.

8.3.13 Digital Signal Filtering

The digital signals have a debounce filtering. The signal or supply is sampled with a clock signal and a counter.

This results as an accuracy of one clock period for the debounce window.

Table 8-7. Digital Signal Filtering

EVENT

SIGNAL/SUPPLY

RISING EDGE

FALLING EDGE

LENGTH

Enable or Disable for BUCKx,

BOOST, or GPOx

ENx

3 µs(1)

VANA undervoltage lockout

VANA

Immediate (VANA voltage rising)

Immediate (VANA voltage falling)

VANA overvoltage

VANA

1 µs (VANA voltage rising)

1 µs (VANA voltage falling)

Thermal warning

TDIE_WARN_INT

20 µs

Thermal shutdown

TDIE_SD_INT

20 µs

Current limit, BUCKx

20 µs

Current limit, BOOST

64 µs

Overload

FB_B0, FB_B1,

VOUT_BST

1 ms

N/V

PGx pin and power-good

interrupt (voltage monitoring)

PG0, PG1 / FB_B0, FB_B1

6 µs

PGx pin and power-good

interrupt (voltage monitoring)

PG0, PG1 / VOUT_BST,

VANA, VMON1, VMON2

15 µs

(1)

No glitch filtering; only synchronization.

8.4 Device Functional Modes

8.4.1 Modes of Operation

SHUTDOWN: The V(VANA) voltage is below the VANAUVLO threshold level or the NRST signal is low. All switch,

reference, control, and bias circuitry of the LP87702-Q1 device are turned off.

READ OTP:

The main supply voltage (V(VANA)) is above the VANAUVLO level and the NRST signal is high.

The converters are disabled and the reference and bias circuitry of the LP87702-Q1 are

enabled. The OTP bits are loaded to the registers. I2C access is not allowed during OTP read.

Section 8.3.8 shows how this also applies to the watchdog.

STANDBY:

The main supply voltage (V(VANA)) is above the VANAUVLO level and the NRST signal is high.

All registers can be read or written by the host processor through the system serial interface.

Watchdog is active and the WDI input is expected to toggle to avoid watchdog expiration. The

converters are disabled and the LP87702-Q1's reference, control, and bias circuitry are enabled.

The converters can be enabled if needed.

ACTIVE:

The main supply voltage (V(VANA)) is above the VANAUVLO level and the NRST signal is high. At

least one converter is enabled. All registers can be read or written by the host processor through

the system's serial interface. Watchdog is active and the WDI input is expected to toggle to avoid

watchdog expiration.

LP87702-Q1

SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021

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