LP87702 datasheet(27/99 Pages) TI

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be set to 10 or 11 to select restart after 2 or 4 WD expirations, respectively. The current status of the

reset counter is available in WD_RESET_CNTR_STATUS.1 The reset counter can be cleared by writing

WD_CLR_RESET_CNTR to 1.

• Watchdog can also be programmed to perform shutdown sequence and enter STOP mode after the

second WD expiration. In STOP mode converters are OFF. WD_RESET output pin is activated for

a period of (10 ms + maximum shutdown delay), in STOP mode WD_RESET is inactive. NRST,

power cycle, register reset SW_RESET, writing WD_CLR_SYSTEM_RESTART_FLAG = 1 or writing

WD_SYSTEM_RESTART_FLAG_MODE = 0 is required to recover. This WD operating mode is selected

by setting OTP bit WD_SYS_RESTART_FLAG_MODE = 1.

Watchdog settings in WD_CTRL_1 and WD_CTRL_2 registers are locked by setting the WD_LOCK bit.

WD_SYSTEM_RESTART_FLAG and WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK = 1.1

Description above is for a case where ENx pin is used for controlling power sequence and ENx pin is active.

Watchdog behavior can be slightly different depending on the OTP settings and the ENx pin state, which follows:

• When the ENx pin is used for controlling the power sequence and the ENx pin is not active, the shutdown

sequence cannot be performed. WD_RESET pulse length is fixed 31 ms.

• There is no OTP defined power sequence when the ENx pins are not used for power sequence control, and

all converters and GPOs are enabled through the I2C. WD expiration does not cause a converter disable

or enable sequence even when the OTP settings for the watchdog enable restart. In this case WD_RESET

pulse is 11 ms.

1 WD_RESET_CNTR_STATUS is valid only when WD_RESET_CNTR_SEL is set to either 00 or 03.

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LP87702-Q1

SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021

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LP87702 датащи(PDF) 27 Page - Texas Instruments