LP87702 datasheet(44/99 Pages) TI

44 / 99 page

ACK from slave

START

MSB Chip Address LSB

SCL

ACK from slave

MSB Register Address LSB

MSB

Data

LSB

STOP

ACK from slave

NACK from master

REPEATED START

Data from slave

SDA

START

id = 0x60

W ACK

address = 0x3F

ACK

R ACK

address 0x3F data

NACK

STOP

MSB Chip Address LSB

id = 0x60

A WRITE function must precede the READ function as shown above when the READ function is accomplished.

Figure 8-19. Read Cycle (r = read; SDA = 1), id = Device Address = 60Hex for LP87702-Q1

8.5.1.4 I2C-Compatible Chip Address

The device address for the LP87702-Q1 is 0x60. After the START condition, the I2C master sends the 7-bit

address followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a

READ. The second byte following the device address selects the register address to which the data will be

written. The third byte contains the data for the selected register.

Bit 7

MSB

LSB

2C Slave Address (chip address)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

R/W

Bit 0

Here device address is 1100000Bin = 60Hex.

Figure 8-20. Device Address

8.5.1.5 Auto Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. The internal

address index counter increments by one and the next register will be written every time an 8-bit word is

sent to the LP87702-Q1. Table 8-8 below shows writing sequence to two consecutive registers. Note: the auto

increment feature does not work for read.

Table 8-8. Auto-Increment Example

MASTER

ACTION

START DEVICE

ADDRESS =

60H

WRITE

ADDRESS

DATA

STOP

LP87702-

ACK

LP87702-Q1

SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021

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