NAND04GA3C2A datasheet(24/51 Pages) STMICROELECTRONICS

24 / 51 page

6 Device operations

NAND04GA3C2A, NAND04GW3C2A

24/51

Figure 10.

Block Erase Operation

6.9

Reset

The Reset command is used to reset the Command Interface and Status Register. If the

Reset command is issued during any operation, the operation will be aborted. If it was a

program or erase operation that was aborted, the contents of the memory locations being

modified will no longer be valid as the data will be partially programmed or erased.

If the device has already been reset then the new Reset command will not be accepted.

The Ready/Busy signal goes Low for tWHBH1 after the Reset command is issued. The value

of tWHBH1 depends on the operation that the device was performing when the command was

issued, refer to Table 20 for the values.

6.10

Read Status Register

The device contains a Status Register which provides information on the current or previous

Program or Erase operation. The various bits in the Status Register convey information and

errors on the operation.

The Status Register is read by issuing the Read Status Register command. The Status

Enable or Read Enable, whichever occurs last. When several memories are connected in a

system, the use of Chip Enable and Read Enable signals allows the system to poll each

device separately, even when the Ready/Busy pins are common-wired. It is not necessary to

toggle the Chip Enable or Read Enable signals to update the contents of the Status

After the Read Status Register command has been issued, the device remains in Read

Status Register mode until another command is issued. Therefore if a Read Status Register

command is issued during a Random Read cycle a new Read command must be issued to

continue with a Page Read operation.

Refer to Table 9 where Status Register bits are summarized. It should also be read in

conjunction with the following text descriptions.

6.10.1

Write Protection Bit (SR7)

The Write Protection bit can be used to identify if the device is protected or not. If the Write

Protection bit is set to ‘1’ the device is not protected and program or erase operations are

allowed. If the Write Protection bit is set to ‘0’ the device is protected and program or erase

operations are not allowed.

I/O

Block Address

Inputs

SR0

ai07593

D0h

70h

60h

Block Erase

Setup Code

Confirm

Code

Read Status Register

Busy

tBLBH3

(Erase Busy time)

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