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NAND04GA3C2A датащи(PDF) 20 Page - STMicroelectronics

номер детали NAND04GA3C2A
подробное описание детали  4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory
PDF  51 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

NAND04GA3C2A датащи(HTML) 20 Page - STMicroelectronics

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6 Device operations
NAND04GA3C2A, NAND04GW3C2A
20/51
Figure 6.
Random Data Output
6.4
Cache Read
The Cache Read operation is used to improve the read throughput by reading data using
the Cache Register. As soon as the user starts to read one page, the device automatically
loads the next page into the Cache Register.
An Cache Read operation consists of three steps (see Table 8):
1.
One bus cycle is required to setup the Cache Read command (the same as the
standard Read command).
2.
Five bus cycles are then required to input the Start Address (refer to Table 6).
3.
One bus cycle is required to issue the Cache Read confirm command to start the P/E/R
Controller.
The Start Address must be at the beginning of a page (Column Address = 000h, see Table
7.). This allows the data to be output uninterrupted after the latency time (tBLBH1), see
Figure 7.
I/O
RB
Address
Inputs
ai08658b
Data Output
Busy
tBLBH1
(Read Busy time)
000h
Cmd
Code
30h
Address
Inputs
Data Output
05h
E0h
5 Add cycles
Main Area
Spare
Area
Col Add 1,2
Row Add 1,2,3
Cmd
Code
Cmd
Code
Cmd
Code
2Add cycles
Main Area
Spare
Area
Col Add 1,2
R



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