NAND04GA3C2A datasheet(23/51 Pages) STMICROELECTRONICS

23 / 51 page

NAND04GA3C2A, NAND04GW3C2A

6 Device operations

23/51

Figure 9.

Random Data Input During Sequential Data Input

6.8

Block Erase

Erase operations are done one block at a time. An erase operation sets all of the bits in the

addressed block to ‘1’. All previous data in the block is lost.

An erase operation consists of three steps (refer to Figure 10:

One bus cycle is required to setup the Block Erase command. Only addresses A19 to

A30 are used, the other address inputs are ignored.

Three bus cycles are then required to load the address of the block to be erased. Refer

to Table 7 for the block addresses of each device.

One bus cycle is required to issue the Block Erase confirm command to start the P/E/R

Controller.

The operation is initiated on the rising edge of write Enable, W, after the confirm command

is issued. The P/E/R Controller handles Block Erase and implements the verify process.

During the Block Erase operation, only the Read Status Register and Reset commands will

be accepted, all other commands will be ignored.

Once the program operation has completed the P/E/R Controller bit SR6 is set to ‘1’ and the

Ready/Busy signal goes High. If the operation completed successfully, the Write Status Bit

SR0 is ‘0’, otherwise it is set to ‘1’.

I/O

Address

Inputs

ai08664

Data Intput

80h

Cmd

Code

Address

Inputs

Data Input

85h

5 Add cycles

Main Area

Spare

Area

Col Add 1,2

Row Add 1,2,3

Cmd

Code

2 Add cycles

Main Area

Spare

Area

Col Add 1,2

Busy

tBLBH2

(Program Busy time)

SR0

10h

70h

Confirm

Code

Read Status Register

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