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NAND02G-B2C датащи(PDF) 46 Page - STMicroelectronics |
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NAND02G-B2C датащи(HTML) 46 Page - STMicroelectronics |
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46 / 62 page ![]() DC And AC parameters NAND01G-B2B, NAND02G-B2C 46/62 Table 25. AC Characteristics for Operations(1) Symbol Alt. Symbol Parameter 1.8V Devices 3V Devices Unit tALLRL1 tAR Address Latch Low to Read Enable Low Read Electronic Signature Min 10 10 ns tALLRL2 Read cycle Min 10 10 ns tBHRL tRR Ready/Busy High to Read Enable Low Min 20 20 ns tBLBH1 Ready/Busy Low to Ready/Busy High Read Busy time Max 25 25 µs tBLBH2 tPROG Program Busy time Max 700 700 µs tBLBH3 tBERS Erase Busy time Max 3 3 ms tBLBH4 Reset Busy time, during ready Max 5 5 µs tBLBH5 tCBSY Cache Busy time Typ 3 3 µs Max 700 700 µs tWHBH1 tRST Write Enable High to Ready/Busy High Reset Busy time, during read Max 5 5 µs Reset Busy time, during program Max 10 10 µs Reset Busy time, during erase Max 500 500 µs tCLLRL tCLR Command Latch Low to Read Enable Low Min 10 10 ns tDZRL tIR Data Hi-Z to Read Enable Low Min 0 0 ns tEHQZ tCHZ Chip Enable High to Output Hi-Z Max 30 30 ns tRHQZ tRHZ Read Enable High to Output Hi-z Max 30 30 ns tWHWH tADL (2) Last Address latched to Data Loading Time during Program operations Min 100 100 ns tVHWH tVLWH tWW (3) Write Protection time Min 100 100 ns tRHRL2 tCRRH Read Enable High hold time during Cache Read operation Min 50 50 ns tELQV tCEA Chip Enable Low to Output Valid Max 45 25 ns tRHRL tREH Read Enable High to Read Enable Low Read Enable High Hold time Min 15 10 ns tEHQX TOH Chip Enable high or Read Enable high to Output Hold Min 10 10 ns tRHQX tRLRH tRP Read Enable Low to Read Enable High Read Enable Pulse Width Min 25 15 ns tRLRL tRC Read Enable Low to Read Enable Low Read Cycle time Min 50 30 ns tRLQV tREA Read Enable Low to Output Valid Read Enable Access time Max 30 20 ns Read ES Access time(4) tWHBH tR Write Enable High to Ready/Busy High Read Busy time Max 25 25 µs tWHBL tWB Write Enable High to Ready/Busy Low Max 100 100 ns tWHRL tWHR Write Enable High to Read Enable Low Min 60 60 ns |
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