NAND02G-B2C datasheet(30/62 Pages) STMICROELECTRONICS

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Device operations

NAND01G-B2B, NAND02G-B2C

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6.6

Block Erase

Erase operations are done one block at a time. An erase operation sets all of the bits in the

addressed block to ‘1’. All previous data in the block is lost.

An erase operation consists of three steps (refer to Figure 14):

One bus cycle is required to setup the Block Erase command. Only addresses A18-

A28 (x8) or A17-A27 (x16) are used, the other address inputs are ignored.

two or three bus cycles are then required to load the address of the block to be erased.

Refer to Table 8 and Table 9 for the block addresses of each device.

one bus cycle is required to issue the Block Erase confirm command to start the P/E/R

Controller.

The operation is initiated on the rising edge of write Enable, W, after the confirm command

is issued. The P/E/R Controller handles Block Erase and implements the verify process.

During the Block Erase operation, only the Read Status Register and Reset commands will

be accepted, all other commands will be ignored.

Once the program operation has completed the P/E/R Controller bit SR6 is set to ‘1’ and the

Ready/Busy signal goes High. If the operation completed successfully, the Write Status Bit

SR0 is ‘0’, otherwise it is set to ‘1’.

Figure 14.

Block Erase Operation

6.7

Reset

The Reset command is used to reset the Command Interface and Status Register. If the

Reset command is issued during any operation, the operation will be aborted. If it was a

program or erase operation that was aborted, the contents of the memory locations being

modified will no longer be valid as the data will be partially programmed or erased.

If the device has already been reset then the new Reset command will not be accepted.

The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value

of tBLBH4 depends on the operation that the device was performing when the command was

issued, refer to Table 25: AC Characteristics for Operations for the values.

I/O

Block Address

Inputs

SR0

ai07593

D0h

70h

60h

Block Erase

Setup Code

Confirm

Code

Read Status Register

Busy

tBLBH3

(Erase Busy time)

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