поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

NAND02G-B2C датащи(PDF) 18 Page - STMicroelectronics

номер детали NAND02G-B2C
подробное описание детали  1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory
PDF  62 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

NAND02G-B2C датащи(HTML) 18 Page - STMicroelectronics

Back Button NAND02G-B2C Datasheet HTML 14Page - STMicroelectronics NAND02G-B2C Datasheet HTML 15Page - STMicroelectronics NAND02G-B2C Datasheet HTML 16Page - STMicroelectronics NAND02G-B2C Datasheet HTML 17Page - STMicroelectronics NAND02G-B2C Datasheet HTML 18Page - STMicroelectronics NAND02G-B2C Datasheet HTML 19Page - STMicroelectronics NAND02G-B2C Datasheet HTML 20Page - STMicroelectronics NAND02G-B2C Datasheet HTML 21Page - STMicroelectronics NAND02G-B2C Datasheet HTML 22Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 18 / 62 page
background image
Bus operations
NAND01G-B2B, NAND02G-B2C
18/62
4.5
Write Protect
Write Protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
4.6
Standby
When Chip Enable is High the memory enters Standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5.
Bus Operations
Bus Operation
E
AL
CL
R
W
WP
I/O0 - I/O7
I/O8 - I/O15(1)
1. Only for x16 devices.
Command Input
VIL
VIL
VIH
VIH
Rising
X(2)
2. WP must be VIH when issuing a program or erase command.
Command
X
Address Input
VIL
VIH
VIL
VIH
Rising
X
Address
X
Data Input
VIL
VIL
VIL
VIH
Rising
VIH
Data Input
Data Input
Data Output
VIL
VIL
VIL
Fallin
g
VIH
X
Data Output
Data Output
Write Protect
X
X
X
X
X
VIL
XX
Standby
VIH
XX
X
X
VIL/VD
D
XX
Table 6.
Address Insertion, x8 Devices
Bus Cycle(1)
1.
Any additional address input cycles will be ignored.
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
A7
A6
A5
A4
A3
A2
A1
A0
2nd
VIL
VIL
VIL
VIL
A11
A10
A9
A8
3rd
A19
A18
A17
A16
A15
A14
A13
A12
4th
A27
A26
A25
A24
A23
A22
A21
A20
5th(2)
2.
The fifth cycle is valid for 2Gb devices. A28 is for 2Gb devices only.
VIL
VIL
VIL
VIL
VIL
VIL
VIL
A28



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com