NAND02G-B2C datasheet(32/62 Pages) STMICROELECTRONICS

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Device operations

NAND01G-B2B, NAND02G-B2C

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6.8.4

Cache Program Error Bit (SR1)

The Cache Program Error bit can be used to identify if the previous page (page N-1) has

been successfully programmed or not in a Cache Program operation. SR1 is set to ’1’ when

the Cache Program operation has failed to program the previous page (page N-1) correctly.

If SR1 is set to ‘0’ the operation has completed successfully.

The Cache Program Error bit is only valid during Cache Program operations, during other

operations it is Don’t Care.

6.8.5

Error Bit (SR0)

The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The

Error Bit is set to ’1’ when a program or erase operation has failed to write the correct data to

the memory. If the Error Bit is set to ‘0’ the operation has completed successfully. The Error

Bit SR0, in a Cache Program operation, indicates a failure on Page N.

6.8.6

SR4, SR3 and SR2 are Reserved

Table 13.

Status Register Bits

Bit

Name

Logic Level

Definition

SR7

Write Protection

'1'

Not Protected

'0'

Protected

SR6

Program/ Erase/ Read

Controller

'1'

P/E/R C inactive, device ready

'0'

P/E/R C active, device busy

Cache Ready/Busy

'1'

Cache Register ready (Cache operation only)

'0'

Cache Register busy (Cache operation only)

SR5

Program/ Erase/ Read

Controller(1)

'1'

P/E/R C inactive, device ready

'0'

P/E/R C active, device busy

SR4, SR3, SR2

Reserved

Don’t Care

SR1

Cache Program Error(2)

'1'

Page N-1 failed in Cache Program operation

'0'

Page N-1 programmed successfully

SR0

Generic Error

‘1’

Error – operation failed

‘0’

No Error – operation successful

Cache Program Error

‘1’

Page N failed in Cache Program operation

‘0’

Page N programmed successfully

Only valid for Cache Program operations, for other operations it is same as SR6.

Only valid for Cache operations, for other operations it is Don’t Care.

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