NAND02G-B2C datasheet(29/62 Pages) STMICROELECTRONICS

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NAND01G-B2B, NAND02G-B2C

Device operations

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6.5

Cache Program

The Cache Program operation is used to improve the programming throughput by

programming data using the Cache Register. The Cache Program operation can only be

used within one block. The Cache Register allows new data to be input while the previous

data that was transferred to the Page Buffer is programmed into the memory array.

The following sequence is required to issue a Cache Program operation (refer to Figure 13):

First of all the program setup command is issued: one bus cycle to issue the program

setup command then 4 or 5 bus write cycles to input the address (see Table 6 and

Table 7). The data is then input (up to 2112 Bytes/ 1056 Words) and loaded into the

Cache Register.

One bus cycle is required to issue the confirm command to start the P/E/R Controller.

The P/E/R Controller then transfers the data to the Page Buffer. During this the device

is busy for a time of tWHBH2.

Once the data is loaded into the Page Buffer the P/E/R Controller programs the data

into the memory array. As soon as the Cache Registers are empty (after tWHBH2) a new

Cache program command can be issued, while the internal programming is still

executing.

Once the program operation has started the Status Register can be read using the Read

Status Register command. During Cache Program operations SR5 can be read to find out

whether the internal programming is ongoing (SR5 = ‘0’) or has completed (SR5 = ‘1’) while

SR6 indicates whether the Cache Register is ready to accept new data. If any errors have

been detected on the previous page (Page N-1), the Cache Program Error Bit SR1 will be set

to ‘1', while if the error has been detected on Page N the Error Bit SR0 will be set to '1’.

When the next page (Page N) of data is input with the Cache Program command, tWHBH2 is

affected by the pending internal programming. The data will only be transferred from the

Cache Register to the Page Buffer when the pending program cycle is finished and the Page

Buffer is available.

If the system monitors the progress of the operation using only the Ready/Busy signal, the

last page of data must be programmed with the Page Program confirm command (10h).

If the Cache Program confirm command (15h) is used instead, Status Register bit SR5 must

be polled to find out if the last programming is finished before starting any other operations.

Figure 13.

Cache Program Operation

Up to 64 pages can be programmed in one Cache Program operation.

tCACHEPG is the program time for the last page + the program time for the (last − 1)

th page

− (Program command cycle time

+ Last page data loading time).

I/O

Address

Inputs

ai08672

80h

Page

Program

Code

Read Status

Busy

Data

Inputs

15h

Cache

Program

Code

80h

Page

Program

Code

15h

Cache Program

Confirm Code

Busy

Last Page

tBLBH5

(Cache Busy time)

tBLBH5

tCACHEPG

SR0

70h

80h

10h

Page

Program

Confirm Code

Busy

First Page

Second Page

(can be repeated up to 63 times)

Address

Inputs

Data

Inputs

Address

Inputs

Data

Inputs

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