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TMPR4925 датащи(PDF) 103 Page - Toshiba Semiconductor

номер детали TMPR4925
подробное описание детали  64-Bit TX System RISC TX49 Family
PDF  590 Pages
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производитель  TOSHIBA [Toshiba Semiconductor]
домашняя страница  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4925 датащи(HTML) 103 Page - Toshiba Semiconductor

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Chapter 5 Configuration Register
5-13
Bits
Mnemonic
Field Name
Description
16
PIOCKE
PIO Clock
Enable
PIO Clock Enable (Initial value: 1, R/W)
This bit controls the PIO clock.
0: Stop clock
1: Supply clock
15:12
Reserved
11
PCIRSTI
PCIC Reset
Inactive
PCIC Reset Inactive (Initial value: 1, R/W)
When this bit is set to “0”, PCIC is reset.
0: Reset
1: normal t
10
DMARSTI
DMAC Reset
Inactive
DMAC Reset Inactive (Initial value: 1, R/W)
When this bit is set to “0”, DMAC is reset.
0: Reset
1: normal
9
Reserved
8SIO0RSTI
SIO0 Reset
Inactive
SIO0 Reset Inactive (Initial value: 1, R/W)
When this bit is set to “0”, SIO0 is reset.
0: Reset
1: normal
7SIO1RSTI
SIO1 Reset
Inactive
SIO1 Reset Inactive (Initial value: 1, R/W)
When this bit is set to “0”, SIO1 is reset.
0: Reset
1: normal
6
TMR0RSTI
TMR0 Reset
Inactive
TMR0 Reset Inactive (Initial value: 1, R/W)
When this bit is set to “0”, TMR0 is reset.
0: Reset
1: normal
5TMR1RSTI
TMR1 Reset
Inactive
TMR1 Reset Inactive (Initial value: 1, R/W)
When this bit is set to “0”, TMR1 is reset.
0: Reset
1: normal
4TMR2RSTI
TMR2 Reset
Inactive
TMR2 Reset Inactive (Initial value: 1, R/W)
When this bit is set to “0”, TMR2 is reset.
0: Reset
1: normal
3
CHIRSTI
CHI Reset
Inactive
CHI Reset Inactive (Initial value: 1, R/W)
When this bit is set to “0”, CHI is reset.
0: Reset
1: normal
2SPIRSTI
SPI Reset
Inactive
SPI Reset Inactive (Initial value: 1, R/W)
When this bit is set to “0”, SPI is reset.
0: Reset
1: normal
1
ACLRSTI
ACLC Reset
Inactive
ACLC Reset Inactive (Initial value: 1, R/W)
When this bit is set to “0”, ACLC is reset.
0: Reset
1: normal
0PIORSTI
PIO Reset
Inactive
PIO Reset Inactive (Initial value: 1, R/W)
When this bit is set to “0”, PIO is reset.
0: Reset
1: normal
Figure 5.2.9 Clock Control Register (CLKCTR) (2/2)



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