TMPR4925 datasheet(7/590 Pages) TOSHIBA

7 / 590 page

Table of Contents

iii

8.3.15

Restrictions in Access to PCI Bus........................................................................................................8-20

8.4

DMA Controller Registers............................................................................................................................8-21

8.4.1

DMA Master Control Register (DMMCR) 0xB0A8 ...........................................................................8-22

8.4.2

DMA Channel Control Register (DMCCRn) 0xB018 (ch. 0), 0xB038 (ch. 1), 0xB058 (ch. 2),

0xB078 (ch. 3) .....................................................................................................................................8-24

8.4.3

DMA Channel Status Register (DMCSRn) 0xB01C (ch. 0), 0xB03C (ch. 1), 0xB05C (ch. 2),

0xB07C (ch. 3).....................................................................................................................................8-28

8.4.4

DMA Source Address Register (DMSARn) 0xB004 (ch. 0), 0xB024 (ch. 1), 0xB044 (ch. 2),

0xB064 (ch. 3) .....................................................................................................................................8-30

8.4.5

DMA Destination Address Register (DMDARn) 0xB008 (ch. 0), 0xB028 (ch. 1), 0xB048 (ch. 2),

0xB068 (ch. 3) .....................................................................................................................................8-31

8.4.6

DMA Chain Address Register (DMCHARn) 0xB000 (ch. 0), 0xB020 (ch. 1), 0xB040 (ch. 2),

0xB060 (ch. 3) .....................................................................................................................................8-32

8.4.7

DMA Source Address Increment Register (DMSAIRn) 0xB010 (ch. 0), 0xB030 (ch. 1),

0xB050 (ch. 2), 0xB070 (ch. 3) ...........................................................................................................8-33

8.4.8

DMA Destination Address Increment Register (DMDAIRn), 0xB014 (ch. 0), 0xB034 (ch. 1),

0xB054 (ch. 2), 0xB074 (ch. 3) ...........................................................................................................8-34

8.4.9

DMA Count Register (DMCNTRn) 0xB00C (ch. 0), 0xB02C (ch. 1), 0xB04C (ch. 2),

0xB06C (ch. 3).....................................................................................................................................8-35

8.4.10

DMA Memory Fill Data Register (DMMFDR) 0xB0A4 ....................................................................8-36

8.5

Timing Diagrams ..........................................................................................................................................8-37

8.5.1

Single Address Single Transfer from Memory to I/O (32-bit ROM)...................................................8-37

8.5.2

Single Address Single Transfer from Memory to I/O (16-bit ROM)...................................................8-38

8.5.3

Single Address Single Transfer from I/O to Memory (32-bit SRAM).................................................8-39

8.5.4

Single Address Burst Transfer from Memory to I/O (32-bit ROM) ....................................................8-40

8.5.5

Single Address Burst Transfer from I/O to Memory (32-bit SRAM) ..................................................8-41

8.5.6

Single Address Single Transfer from Memory to I/O (16-bit ROM)...................................................8-43

8.5.7

Single Address Single Transfer from I/O to Memory (16-bit SRAM).................................................8-44

8.5.8

Single Address Single Transfer from Memory to I/O (32-bit Half Speed ROM) ................................8-45

8.5.9

Single Address Single Transfer from I/O to Memory (32-bit Half Speed SRAM) ..............................8-46

8.5.10

Single Address Single Transfer from Memory to I/O (32-bit SRAM).................................................8-47

8.5.11

Single Address Single Transfer from I/O to Memory (32-bit SDRAM)..............................................8-48

8.5.12

Single Address Single Transfer from Memory to I/O of Last Cycle when DMADONE*

Signal is Set to Output .........................................................................................................................8-49

8.5.13

Single Address Single Transfer from Memory to I/O (32-bit SDRAM)..............................................8-50

8.5.14

Single Address Single Transfer from I/O to Memory (32-bit SDRAM)..............................................8-51

8.5.15

External I/O Device – SRAM Dual Address Transfer .........................................................................8-52

8.5.16

External I/O Device – SDRAM Dual Address Transfer ......................................................................8-54

8.5.17

External I/O Device (Non-burst) – SDRAM Dual Address Transfer...................................................8-56

9. SDRAM Controller .................................................................................................................................................9-1

9.1

Characteristics ................................................................................................................................................9-1

9.2

Block Diagram................................................................................................................................................9-2

9.3

Detailed Explanation ......................................................................................................................................9-3

9.3.1

Supported SDRAM Configurations .......................................................................................................9-3

9.3.2

Address Mapping ...................................................................................................................................9-4

9.3.3

Initialization of SDRAM........................................................................................................................9-9

9.3.4

Low Power Consumption Function .....................................................................................................9-10

9.3.5

Bus Errors ............................................................................................................................................9-11

9.3.6

Memory Read and Memory Write .......................................................................................................9-11

9.3.7

Slow Write Burst..................................................................................................................................9-11

9.3.8

Clock Feedback....................................................................................................................................9-11

9.3.9

SyncFlash ®.........................................................................................................................................9-11

9.4

Registers .......................................................................................................................................................9-12

9.4.1

SDRAM Channel Control Register (SDCCR0) 0x8000 (ch. 0), (SDCCR1) 0x8004 (ch. 1),

(SDCCR2) 0x8008 (ch. 2), (SDCCR3) 0x800C (ch. 3).......................................................................9-13

9.4.2

SDRAM Timing Register (SDCTR) 0x8020 .......................................................................................9-15

9.4.3

SDRAM Command Register (SDCCMD) 0x802C .............................................................................9-17

9.4.4

SyncFlash Command Register (SFCMD) 0x8030 ...............................................................................9-18

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