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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMPR4925 датащи(PDF) 102 Page - Toshiba Semiconductor |
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TMPR4925 датащи(HTML) 102 Page - Toshiba Semiconductor |
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102 / 590 page  Chapter 5 Configuration Register 5-12 5.2.9 Clock Control Register (CLKCTR) 0xE028 For the low-order 16 bits of the clock control register, canceling a reset requires that the corresponding reset bit be cleared by software. Before clearing them, wait at least 128 CPU clock cycles after they are set. 31 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PCICKE DMACKE Reserved SIO0CKE SIO1CKE TMR0CKE TMR1CKE TMR2CKE CHICKE SPICKE ACLCKE PIOCKE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W : Type 11 111 111111 : Initial value 15 12 11 10 9 8 765432 1 0 Reserved PCIRSTI DMARSTI Reserved SIO0RSTI SIO1RSTI TMR0RSTI TMR1RSTI TMR2RSTI CHIRSTI SPIRSTI ACLRSTI PIORSTI R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W : Type 11 111 111111 : Initial value Bits Mnemonic Field Name Description 31:28 Reserved 27 PCICKE PCIC Clock Enable PCIC Clock Enable (Initial value: 1, R/W) This bit controls the PCIC clock. 0: Stop clock 1: Supply clock 26 DMACKE DMAC Clock Enable DMAC Clock Enable (Initial value: 1, R/W) This bit controls the DMAC clock. 0: Stop clock 1: Supply clock 25 Reserved 24 SIO0CKE SIO0 Clock Enable SIO0 Clock Enable (Initial value: 1, R/W) This bit controls the SIO0 clock. 0: Stop clock 1: Supply clock 23 SIO1CKE SIO1 Clock Enable SIO1 Clock Enable (Initial value: 1, R/W) This bit controls the SIO1 clock. 0: Stop clock 1: Supply clock 22 TMR0CKE TMR0 Clock Enable TMR0 Clock Enable (Initial value: 1, R/W) This bit controls the TMR0 clock. 0: Stop clock 1: Supply clock 21 TMR1CKE TMR1 Clock Enable TMR1 Clock Enable (Initial value: 1, R/W) This bit controls the TMR1 clock. 0: Stop clock 1: Supply clock 20 TMR2CKE TMR2 Clock Enable TMR2 Clock Enable (Initial value: 1, R/W) This bit controls the TMR2 clock. 0: Stop clock 1: Supply clock 19 CHICKE CHI Clock Enable CHI Clock Enable (Initial value: 1, R/W) This bit controls the CHI clock. 0: Stop clock 1: Supply clock 18 SPICKE SPI Clock Enable SPI Clock Enable (Initial value: 1, R/W) This bit controls the SPI clock. 0: Stop clock 1: Supply clock 17 ACLCKE ACLC Clock Enable ACLC Clock Enable (Initial value: 1, R/W) This bit controls the ACLC clock. 0: Stop clock 1: Supply clock Figure 5.2.9 Clock Control Register (CLKCTR) (1/2) |
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