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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMPR4925 датащи(PDF) 51 Page - Toshiba Semiconductor |
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TMPR4925 датащи(HTML) 51 Page - Toshiba Semiconductor |
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51 / 590 page  Chapter 1 Features 1-5 1.2.2.6 Timers/Counters Controller (TMR) The TX4925 contains 3-channel timer/counters. • 3-channel 32-bit up-counter • Supports three modes : interval timer mode, pulse generator mode, and watchdog timer mode • 2 timer output pins • 1 count clock input pin 1.2.2.7 Parallel I/O Ports (PIO) The TX4925 contains 32-bit parallel I/O ports • Independent selection of direction of pins and output port type (totem-pole or open-drain outputs) on a per bit basis. 1.2.2.8 AC-Link Controller (ACLC) AC-Link Controller in TX4925 can be connected to audio and/or modem CODECs described in the “Audio CODEC ’97 Revision 2.1” (AC’97) and can operate them. • AC97 2.1 compliant CODEC register access protocol • Up to two CODECs are supported • Support Audio CODEC (Recording/Playback of 16-bit PCM Left/Right channels) − Support Playback of 16-bit Surround, Center, and LFE channels − Support Variable Rate Audio recording/Playback • Support Modem CODEC (Line 1 and GPIO slots) • Support AC-link low-power mode, wake-up, and warm-reset • Support sample-data I/O via DMA transfer 1.2.2.9 Interrupt Controller (IRC) Interrupt controller in TX4925 supports both internal and external interrupts to the processor core. The priority or the value of each interrupt source is programmed in interrupt level registers. It has a 16-bit flag register to generate interrupt requests to external devices or the TX49/H2 core. • Priority process of 21 internal and up to 8 external interrupt sources. − PCIC, DMAC, SIO, Timer Interrupts, RTC, NAND Flash Controller, ACLC, SPI, CHI, PIO and External Interrupts − All of external interrupt signals shares other function signals • Edge/Level selectable trigger interrupt • Support of Non Mask-able interrupt (NMI) • 16-bit read/write flag register for interrupt requests, making it possible to issue interrupt requests to external devices and to the TX49/H2 core (IRC interrupts) |
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