TMPR4925 datasheet(49/590 Pages) TOSHIBA

49 / 590 page

Chapter 1 Features

1-3

1.2.2

TX4925 Peripheral Circuit Features

1.2.2.1

External Bus Controller (EBUSC)

The External Bus Controller generates necessary signals to control external memory and

I/O devices.

•

6 channels of chip select signals, enabling control of up to six devices

•

Supports access to ROM ( including mask ROM, page mode ROM, EPROM and EEPROM),

SRAM, flash ROM, and I/O devices

•

Supports 32-bit, 16-bit and 8-bit data bus sizing on a per channel basis

•

Supports selection among full speed (up to 80 MHz), 1/2 speed (up to 40 MHz), 1/3 speed

(up to 27 MHz) and 1/4 speed (up to 20 MHz) on a per channel basis

•

Support specification of timing on a per channel basis

•

The user can specify setup and hold times for address, chip enable, write enable, and output

enable signals

•

Supports memory sizes of 1M byte to 1G byte for devices with 32-bit data bus, 1M byte to

512M bytes for devices with 16-bit data bus, and 1M byte to 256M bytes for devices with 8-

bit data bus

1.2.2.2

DMA Controller (DMAC)

The TX4925 contains a 4-channel DMA controller that executes DMA transfer to memory and

I/O devices.

•

4-channel independently handling internal/external DMA requests

(Usable 2 channels by external DMA requests)

•

Supports DMA transfer with built-in serial I/O controller and AC-link controller based on

internal DMA requests

•

Supports signal address (fly-by DMA) and dual address transfers in external I/O DMA

transfer mode using external DMA requests

•

Supports transfer between memory and external I/O devices having 32-/16-/8-bit data bus

•

Supports memory-to-memory copy mode, with no address boundary restrictions

•

Supports burst transfer of up to 8 words for a single read/write

•

Supports memory fill mode, writing word data to specified memory area

•

Supports chained DMA transfer

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