TMPR4925 datasheet(63/590 Pages) TOSHIBA

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Chapter 3 Signals

3-5

3.1.4

DMA Interface Signals

Table 3.1.4 DMA Interface Signals

Signal Name

Type

Description

Initial State

DMAREQ[1:0]

Input

DMA Request

DMA transfer request signals from an external I/O device.

The pins are shared with other functions (refer to Section "3.3 Pin Multiplexing").

PIO input

DMAACK[1:0]

Output

DMA Acknowledge

DMA transfer acknowledge signals to an external I/O device.

The pins are shared with other functions (refer to Section "3.3 Pin Multiplexing").

PIO input

DMADONE*

Input/output

DMA Done

DMADONE* is either used as an output signal that reports the termination of DMA

transfer or as an input signal that causes DMA transfer to terminate.

The pin is shared with other functions (refer to Section "3.3 Pin Multiplexing").

PIO input

3.1.5

PCI Interface Signals

Table 3.1.5 PCI Interface Signals (1/2)

Signal Name

Type

Description

Initial State

PCICLK[2:1]

Output

PCI Clock

PCI bus clock signals.

A boot configuration signal (ADDR[18]) can determine whether the clock internally

generated in the TX4925 is used as PCICLK. If the TX4925 internal clock is selected,

the clock signals are output from these pins.

When these clock signals are not used, the pins can be set to High-Z using the

PCICLK Enable field of the pin configuration register (PCFG.PCICLKEN[2:1]).

Selected by

ADDR[18]

H: High

L: L

PCICLKIO

Input/output

PCI Feedback Clock

PCI feedback clock input.

A boot configuration signal (ADDR[18]) can determine whether the clock internally

generated in the TX4925 is used as PCICLK. If the TX4925 internal clock is selected,

the clock signals are output and simultaneously fed back to the internal PCI block.

When using the PCI block, therefore, do not set the PCICLK Enable field of the pin

configuration register (PCFG.PCICLKIOEN) to 0.

Selected by

ADDR[18]

H: High

L: Input

PCIAD[31:0]

Input/output

PCI Address and Data

Multiplexed address and data bus.

Input

C_BE[3:0]

Input/output

Command and Byte Enable

Command and byte enable signals.

Input

PAR

Input/output

Parity

Even parity signal for PCIAD[31:0] and C_BE[3:0]*.

Input

FRAME*

Input/output

Cycle Frame

Indicates that bus operation is in progress.

Input

IRDY*

Input/output

Initiator Ready

Indicates that the initiator is ready to complete data transfer.

Input

TRDY*

Input/output

Target Ready

Indicates that the target is ready to complete data transfer.

Input

STOP*

Input/output

Stop

The target sends this signal to the initiator to request termination of data transfer.

Input

ID_SEL

Input

Initialization Device Select

Chip select signal used for configuration access.

Input

DEVSEL*

Input/output

Device Select

The target asserts this signal in response to access from the initiator.

Input

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