TMPR4925 datasheet(8/590 Pages) TOSHIBA

8 / 590 page

Table of Contents

9.5

Timing Diagrams ..........................................................................................................................................9-19

9.5.1

Single Read (32-bit Bus)......................................................................................................................9-19

9.5.2

Single Write (32-bit Bus) .....................................................................................................................9-21

9.5.3

Burst Read (32-bit Bus) .......................................................................................................................9-23

9.5.4

Burst Write (32-bit Bus) ......................................................................................................................9-24

9.5.5

Burst Write (32-bit Bus, Slow Write Burst) .........................................................................................9-25

9.5.6

Single Read (16-bit Bus)......................................................................................................................9-26

9.5.7

Single Write (16-bit Bus) .....................................................................................................................9-28

9.5.8

Low Power Consumption and Power Down Mode..............................................................................9-30

9.6

SDRAM Usage Example..............................................................................................................................9-34

10. PCI Controller .......................................................................................................................................................10-1

10.1

Features.........................................................................................................................................................10-1

10.1.1

Overall .................................................................................................................................................10-1

10.1.2

Initiator Function .................................................................................................................................10-1

10.1.3

Target Function ....................................................................................................................................10-1

10.1.4

PCI Arbiter...........................................................................................................................................10-2

10.1.5

PDMAC (PCI DMA Controller)..........................................................................................................10-2

10.2

Block Diagram..............................................................................................................................................10-3

10.3

Detailed Explanation ....................................................................................................................................10-4

10.3.1

Terminology Explanation.....................................................................................................................10-4

10.3.2

On-Chip Register .................................................................................................................................10-4

10.3.3

Supported PCI Bus Commands............................................................................................................10-6

10.3.4

Initiator Access (G-Bus

→ PCI Bus address conversion)....................................................................10-8

10.3.5

Target Access (PCI Bus

→ G-Bus Address Conversion)...................................................................10-10

10.3.6

Post Write Function ...........................................................................................................................10-13

10.3.7

Endian Switching Function................................................................................................................10-13

10.3.8

Power Management ...........................................................................................................................10-14

10.3.9

PDMAC (PCI DMA Controller)........................................................................................................10-15

10.3.10 Error Detection, Interrupt Reporting..................................................................................................10-18

10.3.11 PCI Bus Arbiter .................................................................................................................................10-20

10.3.12 PCI Boot ............................................................................................................................................10-22

10.3.13 Set Configuration Space ....................................................................................................................10-22

10.3.14 PCI Clock Signal................................................................................................................................10-22

10.4

PCI Controller Control Register .................................................................................................................10-23

10.4.1

ID Register (PCIID) 0xD000 .............................................................................................................10-25

10.4.2

PCI Status, Command Register (PCISTATUS) 0xD004....................................................................10-26

10.4.3

Class Code, Revision ID Register (PCICCREV) 0xD008 .................................................................10-28

10.4.4

PCI Configuration 1 Register (PCICFG1) 0xD00C...........................................................................10-29

10.4.5

P2G Memory Space 0 PCI Base Address Register (P2GM0PBASE) 0xD010..................................10-30

10.4.6

P2G Memory Space 1 PCI Base Address Register (P2GM1PBASE) 0xD014..................................10-31

10.4.7

P2G Memory Space 2 PCI Base Address Register (P2GM2PBASE) 0xD018..................................10-32

10.4.8

P2G I/O Space PCI Base Address Register (P2GIOPBASE) 0xD01C..............................................10-33

10.4.9

Subsystem ID Register (PCISID) 0xD02C ........................................................................................10-34

10.4.10 Capabilities Pointer Register (PCICAPPTR) 0xD034 .......................................................................10-35

10.4.11 PCI Configuration 2 Register (PCICFG2) 0xD03C...........................................................................10-36

10.4.12 G2P Timeout Count Register (G2PTOCNT) 0xD040 .......................................................................10-37

10.4.13 G2P Configuration Register (G2PCFG) 0xD060..............................................................................10-38

10.4.14 G2P Status Register (G2PSTATUS) 0xD064.....................................................................................10-40

10.4.15 G2P Interrupt Mask Register (G2PMASK) 0xD068 .........................................................................10-41

10.4.16 Satellite Mode PCI Status Register (PCISSTATUS) 0xD088 ............................................................10-42

10.4.17 PCI Status Interrupt Mask Register (PCIMASK) 0xD08C................................................................10-43

10.4.18 P2G Configuration Register (P2GCFG) 0xD090...............................................................................10-44

10.4.19 P2G Status Register (P2GSTATUS) 0xD094.....................................................................................10-45

10.4.20 P2G Interrupt Mask Register (P2GMASK) 0xD098 .........................................................................10-46

10.4.21 P2G Current Command Register (P2GCCMD) 0xD09C...................................................................10-47

10.4.22 PCI Bus Arbiter Request Port Register (PBAREQPORT) 0xD100...................................................10-48

10.4.23 PCI Bus Arbiter Configuration Register (PBACFG) 0xD104 ...........................................................10-50

10.4.24 PCI Bus Arbiter Status Register (PBASTATUS) 0xD108 .................................................................10-51

TMPR4925 датащи(PDF) 8 Page - Toshiba Semiconductor

TMPR4925 датащи(HTML) 8 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL