TMPR4925 datasheet(12/590 Pages) TOSHIBA

12 / 590 page

Table of Contents

viii

15.4.10 Interrupt Level Register 6 (IRLVL6) 0xF628 ....................................................................................15-20

15.4.11 Interrupt Level Register 7 (IRLVL7) 0xF62C ...................................................................................15-21

15.4.12 Interrupt Mask Level Register (IRMSK) 0xF640 ..............................................................................15-22

15.4.13 Interrupt Edge Detection Clear Register (IREDC) 0xF660 ...............................................................15-23

15.4.14 Interrupt Pending Register (IRPND) 0xF680 ....................................................................................15-24

15.4.15 Interrupt Current Status Register (IRCS) 0xF6A0 .............................................................................15-27

15.4.16 Interrupt Request Flag Register 0 (IRFLAG0) 0xF510 .....................................................................15-29

15.4.17 Interrupt Request Flag Register 1 (IRFLAG1) 0xF514 .....................................................................15-29

15.4.18 Interrupt Request Polarity Control Register (IRPOL) 0xF518 ..........................................................15-30

15.4.19 Interrupt Request Control Register (IRRCNT) 0xF51C ....................................................................15-30

15.4.20 Interrupt Request Internal Interrupt Mask Register (IRMASKINT) 0xF520 ....................................15-31

15.4.21 Interrupt Request External Interrupt Mask Register (IRMASKEXT) 0xF524 ..................................15-31

16. CHI Module...........................................................................................................................................................16-1

16.1

Characteristics ..............................................................................................................................................16-1

16.2

Block Diagram..............................................................................................................................................16-2

16.3

Detailed Explanation ....................................................................................................................................16-3

16.3.1

Transmitter ...........................................................................................................................................16-3

16.3.2

Receiver ...............................................................................................................................................16-4

16.3.3

Clock and Control Generation .............................................................................................................16-4

16.3.4

DMA Address Generation ...................................................................................................................16-6

16.3.5

Timing Diagram...................................................................................................................................16-8

16.3.6

Interrupts..............................................................................................................................................16-9

16.3.7

Frame Structure and Serial Timing ....................................................................................................16-10

16.3.8

Configurations ...................................................................................................................................16-16

16.4

CHI Registers .............................................................................................................................................16-17

16.4.1

CHI Control Register (CTRL) 0xA800..............................................................................................16-18

16.4.2

CHI Pointer Enable Register (PNTREN) 0xA804 ............................................................................16-21

16.4.3

CHI Receive Pointer A Register (RXPTRA) 0xA808 .......................................................................16-23

16.4.4

CHI Receive Pointer B Register (RXPTRB) 0xA80C.......................................................................16-24

16.4.5

CHI Transmit Pointer A Register (TXPTRA) 0xA810 ......................................................................16-25

16.4.6

CHI Transmit Pointer B Register (TXPTRB) 0xA814 ......................................................................16-26

16.4.7

CHI SIZE Register (CHISIZE) 0xA818 ............................................................................................16-27

16.4.8

CHI RX Start Register (RXSTRT) 0xA81C ......................................................................................16-28

16.4.9

CHI TX Start Register (TXSTRT) 0xA820 .......................................................................................16-29

16.4.10 CHI TX Holding Register (CHIHOLD) 0xA824...............................................................................16-30

16.4.11 CHI RX Holding Register (CHIHOLD) 0xA824 ..............................................................................16-31

16.4.12 CHI Clock Register (CHICLOCK) 0xA828 ......................................................................................16-32

16.4.13 HI Interrupt Enable Register (CHIINTE) 0xA82C ............................................................................16-33

16.4.14 CHI Interrupt Status Register (CHIINT) 0xA830..............................................................................16-34

17. Serial Peripheral Interface (SPI)............................................................................................................................17-1

17.1

Characteristics ..............................................................................................................................................17-1

17.2

Block Diagram..............................................................................................................................................17-2

17.3

Detailed Explanation ....................................................................................................................................17-3

17.3.1

Operation mode....................................................................................................................................17-3

17.3.2

Transmitter/Receiver............................................................................................................................17-3

17.3.3

Baud Rate Generator............................................................................................................................17-4

17.3.4

Transfer Format....................................................................................................................................17-5

17.3.5

Inter Frame Space Counter ..................................................................................................................17-6

17.3.6

SPI Buffer Structure.............................................................................................................................17-7

17.3.7

SPI System Errors ................................................................................................................................17-7

17.3.8

Interrupts..............................................................................................................................................17-7

17.4

Registers .......................................................................................................................................................17-8

17.4.1

SPI Master Control Register (SPMCR) 0xF800 ..................................................................................17-9

17.4.2

SPI Control Register 0 (SPCR0) 0xF804...........................................................................................17-10

17.4.3

SPI Control Register 1 (SPCR1) 0xF808...........................................................................................17-12

17.4.4

SPI Inter Frame Space Register (SPFS) 0xF80C ...............................................................................17-13

17.4.5

SPI Status Register (SPSR) 0xF814...................................................................................................17-14

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