TMPR4925 datasheet(71/590 Pages) TOSHIBA

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Chapter 3 Signals

3-13

Table 3.2.2 Boot Configuration Specified with the ADDR[19:0], TDO, UAE and SADDR10 Signals (1/2)

Signal

Description

Corresponding

Configuration

Determined at

ADDR[19]

Reserved

This signal will be set to 0 upon booting.

CCFG bit [12]

RESET* deassert

edge

ADDR[18]

PCI Clock Enable

Specifies whether the clock generated by the TX4925 internal clock

generator is used as a PCI clock.

L = Use a PCI clock input from an external device.

The PCI clock is input via PCICLKIO.

PCICLK[2:1] are placed in High-Z state.

H = Use a clock generated by the TX4925 clock generator.

The clock is output from PCICLK[2:1] and PCICLKIO. The clock output

from PCICLKIO is fed back for use with the internal PCIC.

PCFG. PCICLKEN

PON* deassert edge

ADDR[17:16]

Reserved

Used for testing. Because this signal is used for setting a clock

frequency, ensure that the signal will not be set to 0 upon booting.

CCFG.bit[18](ADDR[

17])

CCFG.bit[27](ADDR[

16])

PON* deassert edge

ADDR[15]

PCI Controller Mode Select

Specifies the operating mode of the TX4925 PCI controller.

L = Satellite

H = Host

CCFG. PCIMODE

RESET* deassert

edge

ADDR[14]

TX4925 Endian Mode

Specifies the TX4925 endian mode.

L = Little endian

H = Big endian

CCFG. ENDIAN

RESET* deassert

edge

ADDR[13:12]

Boot ROM Bus Width

Specifies the data bus width when booting from a memory device

connected to the external memory controller. If SyncFlash is selected

as a boot memory device, refer to Table 3.2.3.

LL = Reserved

LH = 32 bits

HL = 16 bits

HH = 8 bits

EBCCR0.BSZ

RESET* deassert

edge

ADDR[11]

Boot Byte Enable Type

When booting from a memory device connected to the external

memory controller, specifies the function of the BE[3:0]*/BWE[3:0]*

pins upon booting. Be sure that this bit does not become “0” when

booting from PCL.

L = BE[3:0]* (Byte Enable)

H = BWE[3:0]* (Byte Write Enable)

When booting from SyncFlash

Refer to Table 3.2.3.

EBCCR0.BC

RESET* deassert

edge

ADDR[10]

Reserved

Used for testing. Setting this signal to 0 disables TCK, TDI, TMS,

TRST* and TDO. Ensure that the signal will not be set to 0 upon

booting.

CCFG.bit[31]

RESET* deassert

edge

ADDR[9]

Reserved

This signal will not be set to 0 upon booting.



RESET* deassert

edge

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