TMPR4925 datasheet(64/590 Pages) TOSHIBA

64 / 590 page

Chapter 3 Signals

3-6

Table 3.1.5 PCI Interface Signals (2/2)

Signal Name

Type

Description

Initial State

REQ[3:2]*

Input

Request

Signals used by the master to request bus mastership.

The boot configuration signal on the ADDR[1] pin determines whether the built-in PCI bus

arbiter is used.

In internal arbiter mode, REQ[3:2]* are PCI bus request input signals.

In external arbiter mode, REQ[3:2]* are not used. Because the pins are still placed in the

input state, they must be pulled up externally.

Input

REQ[1]*

/INTOUT

Input/output/

Request

Signal used by the master to request bus mastership.

The boot configuration signal on the ADDR[1] pin determines whether the built-in PCI bus

arbiter is used.

In internal arbiter mode, this signal is a PCI bus request input signal.

In external arbiter mode, this signal is an external interrupt output signal (INTOUT). Refer

to Section “15.3.7 Interrupt Requests”.

Selected by

ADDR[1]

H: Input

L: High-Z

REQ[0]*

Input/output

Request

Signal used by the master to request bus mastership.

The boot configuration signal on the ADDR[1] pin determines whether the built-in PCI bus

arbiter is used.

In internal arbiter mode, this signal is a PCI bus request input signal.

In external arbiter mode, this signal is a PCI bus request output signal.

Selected by

ADDR[1]

H: Input

L: High

GNT[3:0]*

Input/output

Grant

Indicates that bus mastership has been granted to the PCI bus master.

The boot configuration signal on the ADDR[1] pin determines whether the built-in PCI bus

arbiter is used.

In internal arbiter mode, all of GNT[3:0]* are PCI bus grant output signals.

In external arbiter mode, GNT[0]* is a PCI bus grant input signal. Because GNT[3:1]*

also become input signals, they must be pulled up externally.

Selected by

ADDR[1]

H: All High

L: Input

PERR*

Input/output

Data Parity Error

Indicates a data parity error in a bus cycle other than special cycles.

Input

SERR*

Input/OD

System Error

Indicates an address parity error, a data parity error in a special cycle, or a fatal error.

In host mode, SERR* is an input signal. In satellite mode, SERR* is an open-drain output

signal. The mode is determined by the boot configuration signal on the ADDR[19] pin.

Input

TMPR4925 датащи(PDF) 64 Page - Toshiba Semiconductor

TMPR4925 датащи(HTML) 64 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL