TMPR4925 datasheet(96/590 Pages) TOSHIBA

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Chapter 5 Configuration Register

5-6

5.2.3

Pin Configuration Register (PCFG)

0xE008

For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial

input signal level and the corresponding register value are indicated.

SYSCLKEN

SDRCLKEN

PCICLKEN

PCICLKIOEN

Reserved

Reserved SELSPI

SELCHI

SELCARD

SELCE

R/W

: Type

ADDR[18]

: Initial value

SELSIOC

SELSIO

ACKIN

SELTMR

SELDONE

Reserved

SELACLC SELNAND

SELDMA

R/W

: Type

001

000

0000

: Initial value

Bits

Mnemonic

Field Name

Description

SYSCLKEN

SYSCLK

Enable

SYSCLK Enable (Initial value: 1, R/W)

Specifies whether to output the SYSCLK.

1: Clock output.

0: L.

30:29

SDRCLKEN

[1:0]

SDRAM Clock

Enable

SDRAM Clock Enable (Initial value: 11, R/W)

Individually specifies whether to output each of SDCLK [1:0].

1: Clock output.

0: L.

Bit 30 = SDCLK [1]

Bit 29 = SDCLK [0]

28:27

PCICLKEN

[2:0]

PCI Clock Enable

PCI Clock Enable (Initial value: ADDR[18], R/W)

Individually specifies whether to output each of PCICLK [2:1].

1: Clock output.

0: L.

Bit 28 = PCICLK [2]

Bit 27 = PCICLK [1]

PCICLKIOEN

PCI Clock I/O

Enable

PCI Clock I/O Enable (Initial value: ADDR[18], R/W)

Individually specifies whether to output each of PCICLK [2:1].

1: Clock output.

0: Clock input.

25:23



Reserved



Reserved

Note: This bit is always set to “0” (Initial value: 0, R/W).

SELSPL

Select SPI

Select SPI (Initial value: 0, R/W)

Select SPI function as PIO[23:21] pin. Please refer to “3.3 Pin Multiplexing” about

setting.

SELCHI

Select CHI

Select CHI (Initial value: 0, R/W)

Select SPI function as PIO[27,20:18] pin. Please refer to “3.3 Pin Multiplexing”

about setting.

19:18

SELCARD

Select PCMCIA

CARD

Select PCMCIA CARD (Initial value: 00, R/W)

Select PCMCIA CARD function as PIO[31:24] pin. Please refer to “3.3 Pin

Multiplexing” about setting.

17:16

SELCE

Select CE[5:4]*

Select CE[5:4]* (Initial value: 00, R/W)

Select CE[5:4]* function as PIO[29:28] pin. Please refer to “3.3 Pin Multiplexing”

about setting.

15:14

SELSIOC

Select SIO

Control Pins

Select SIO Control Pins (Initial value: 00, R/W)

Select SIO ch1, 0 control signals (RTS, CTS) as PIO[15,14,9,8] pin. Please refer to

“3.3 Pin Multiplexing” about setting.

13:12

SELSIO

Select SIO

Select SIO (Initial value: 00, R/W)

Select SIO ch1, 0 signals (TXD, RXD) as PIO[17,16,11,10] pin. Please refer to “3.3

Pin Multiplexing” about setting.

ACKIN

ACK* input

ACK* input (Initial value: 1, R/W)

When this bit is one, ACK* signal is input.

0 : ACK* pin changes from input to output dynamically based on EBUSC channel

settings.

1 : ACK* pin is input only.

Figure 5.2.3 Pin Configuration Register (PCFG) (1/2)

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