Z8F082ASH020SC datasheet(59/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

General-Purpose I/O

Z8 Encore! XP® F08xA Series

Product Specification

PHDE[7:0]—Port High Drive Enabled

0 = The Port pin is configured for standard output current drive.

1 = The Port pin is configured for high output current drive.

Port A–D STOP Mode Recovery Source Enable Sub-Registers

The Port A–D STOP Mode Recovery Source Enable sub-register (Table 22) is accessed

through the Port A–D Control register by writing 05H to the Port A–D Address register.

Setting the bits in the Port A–D STOP Mode Recovery Source Enable sub-registers to 1

configures the specified Port pins as a STOP Mode Recovery source. During STOP Mode,

any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates

STOP Mode Recovery.

PSMRE[7:0]—Port STOP Mode Recovery Source Enabled

0 = The Port pin is not configured as a STOP Mode Recovery source. Transitions on this

pin during STOP mode do not initiate STOP Mode Recovery.

1 = The Port pin is configured as a STOP Mode Recovery source. Any logic transition on

this pin during STOP mode initiates STOP Mode Recovery.

Port A–D Pull-up Enable Sub-Registers

The Port A–D Pull-up Enable sub-register (Table 23) is accessed through the Port A–D

Control register by writing 06H to the Port A–D Address register. Setting the bits in the

Port A–D Pull-up Enable sub-registers enables a weak internal resistive pull-up on the

specified Port pins.

Table 22. Port A–D STOP Mode Recovery Source Enable Sub-Registers (PxSMRE)

BITS

FIELD

PSMRE7

PSMRE6

PSMRE5

PSMRE4

PSMRE3

PSMRE2

PSMRE1

PSMRE0

RESET

000

R/W

R/WR/W

ADDR

If 05H in Port A–D Address Register, accessible through the Port A–D Control Register

Table 23. Port A–D Pull-Up Enable Sub-Registers (PxPUE)

BITS

FIELD

PPUE7

PPUE6

PPUE5

PPUE4

PPUE3

PPUE2

PPUE1

PPUE0

RESET

000

R/W

R/WR/W

ADDR

If 06H in Port A

–D Address Register, accessible through the Port A–D Control Register

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