Z8F082ASH020SC datasheet(94/244 Pages) ZILOG

94 / 244 page

PS024705-0405

P R E L I M I N A R Y

Timers

Z8 Encore! XP® F08xA Series

Product Specification

When the timer is enabled, the Timer Output signal is complemented upon timer

Reload.

CONTINUOUS mode

When the timer is disabled, the Timer Output signal is set to the value of this bit.

When the timer is enabled, the Timer Output signal is complemented upon timer

Reload.

COUNTER mode

When the timer is disabled, the Timer Output signal is set to the value of this bit.

When the timer is enabled, the Timer Output signal is complemented upon timer

Reload.

PWM SINGLE OUTPUT mode

0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the

Timer Output is forced High (1) upon PWM count match and forced Low (0) upon

Reload.

1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the

Timer Output is forced Low (0) upon PWM count match and forced High (1) upon

Reload.

CAPTURE mode

0 = Count is captured on the rising edge of the Timer Input signal.

1 = Count is captured on the falling edge of the Timer Input signal.

COMPARE mode

When the timer is disabled, the Timer Output signal is set to the value of this bit.

When the timer is enabled, the Timer Output signal is complemented upon timer

Reload.

GATED mode

0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated

on the falling edge of the Timer Input.

1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated

on the rising edge of the Timer Input.

CAPTURE/COMPARE mode

0 = Counting is started on the first rising edge of the Timer Input signal. The current

count is captured on subsequent rising edges of the Timer Input signal.

1 = Counting is started on the first falling edge of the Timer Input signal. The current

count is captured on subsequent falling edges of the Timer Input signal.

PWM DUAL OUTPUT mode

0 = Timer Output is forced Low (0) and Timer Output Complement is forced High (1)

when the timer is disabled. When enabled, the Timer Output is forced High (1) upon

PWM count match and forced Low (0) upon Reload. When enabled, the Timer Output

Complement is forced Low (0) upon PWM count match and forced High (1) upon

Reload. The PWMD field in TxCTL0 register is a programmable delay to control the

Z8F082ASH020SC датащи(PDF) 94 Page - Zilog, Inc.

Z8F082ASH020SC датащи(HTML) 94 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL