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Z8F082ASH020SC датащи(PDF) 71 Page - Zilog, Inc.

номер детали Z8F082ASH020SC
подробное описание детали  Z8 Encore XP-R F08xA Series with eXtended Peripherals
PDF  244 Pages
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производитель  ZILOG [Zilog, Inc.]
домашняя страница  http://www.zilog.com
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Z8F082ASH020SC датащи(HTML) 71 Page - Zilog, Inc.

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PS024705-0405
P R E L I M I N A R Y
Interrupt Controller
Z8 Encore! XP® F08xA Series
Product Specification
53
IRQ0 Enable High and Low Bit Registers
Table 35 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg-
isters (Tables 36 and 37) form a priority encoded enabling for interrupts in the Interrupt
Request 0 register. Priority is generated by setting bits in each register.
Reserved—Must be 0.
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
Reserved—Must be 0.
Table 35. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
where x indicates the register bits from 0–7.
Table 36. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS
7
6
5
4
3
2
1
0
FIELD
Reserved
T1ENH
T0ENH
U0RENH
U0TENH
Reserved
Reserved
ADCENH
RESET
0
000
00
00
R/W
R/WR/W
R/WR/W
R/WR/W
R/WR/W
ADDR
FC1H
Table 37. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
7
6
5
4
3
2
1
0
FIELD
Reserved
T1ENL
T0ENL
U0RENL
U0TENL
Reserved
Reserved
ADCENL
RESET
0
000
00
00
R/W
R
R/W
R/W
R/W
R/W
R
R
R/W
ADDR
FC2H



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