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Z8F082ASH020SC датащи(PDF) 72 Page - Zilog, Inc.

номер детали Z8F082ASH020SC
подробное описание детали  Z8 Encore XP-R F08xA Series with eXtended Peripherals
PDF  244 Pages
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производитель  ZILOG [Zilog, Inc.]
домашняя страница  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8F082ASH020SC датащи(HTML) 72 Page - Zilog, Inc.

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PS024705-0405
P R E L I M I N A R Y
Interrupt Controller
Z8 Encore! XP® F08xA Series
Product Specification
54
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
Table 38 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg-
isters (Tables 39 and 40) form a priority encoded enabling for interrupts in the Interrupt
Request 1 register. Priority is generated by setting bits in each register.
PA6CENH—Port A Bit[6] or Comparator Interrupt Request Enable High Bit
PAxENH—Port A Bit[x] Interrupt Request Enable High Bit
Refer to the Shared Interrupt Select register for selection of either Port A or Port D as the
interrupt source.
Table 38. IRQ1 Enable and Priority Encoding
IRQ1ENH[x]IRQ1ENL[x] Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
11
Level 3
High
where x indicates the register bits from 0–7.
Table 39. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS
7
6
5
4
3
2
1
0
FIELD
PA7ENH
PA6CENH
PA5ENH
PA4ENH
PA3ENH
PA2ENH
PA1ENH
PA0ENH
RESET
0
000
00
00
R/W
R/WR/W
R/WR/W
R/WR/W
R/WR/W
ADDR
FC4H



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