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Z8F082ASH020SC датащи(PDF) 56 Page - Zilog, Inc.

номер детали Z8F082ASH020SC
подробное описание детали  Z8 Encore XP-R F08xA Series with eXtended Peripherals
PDF  244 Pages
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производитель  ZILOG [Zilog, Inc.]
домашняя страница  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8F082ASH020SC датащи(HTML) 56 Page - Zilog, Inc.

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PS024705-0405
P R E L I M I N A R Y
General-Purpose I/O
Z8 Encore! XP® F08xA Series
Product Specification
38
PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control reg-
ister.
Port A–D Control Registers
The Port A–D Control registers set the GPIO port operation. The value in the correspond-
ing Port A–D Address register determines which sub-register is read from or written to by
a Port A–D Control register transaction (Table 17).
PCTL[7:0]—Port Control
The Port Control register provides access to all sub-registers that configure the GPIO Port
operation.
Port A–D Data Direction Sub-Registers
The Port A–D Data Direction sub-register is accessed through the Port A–D Control regis-
ter by writing 01H to the Port A–D Address register (Table 18).
PADDR[7:0]
Port Control sub-register accessible using the Port A–D Control Registers
00H
No function. Provides some protection against accidental Port reconfiguration.
01H
Data Direction
02H
Alternate Function
03H
Output Control (Open-Drain)
04H
High Drive Enable
05H
STOP Mode Recovery Source Enable.
06H
Pull-up Enable
07H
Alternate Function Set 1
08H
Alternate Function Set 2
09H–FFH
No function
Table 17. Port A–D Control Registers (PxCTL)
BITS
7
6
5
4
3
2
1
0
FIELD
PCTL
RESET
00H
R/W
R/WR/W
R/WR/W
R/WR/W
R/WR/W
ADDR
FD1H, FD5H, FD9H, FDDH



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