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Z8F082ASH020SC датащи(PDF) 33 Page - Zilog, Inc.

номер детали Z8F082ASH020SC
подробное описание детали  Z8 Encore XP-R F08xA Series with eXtended Peripherals
PDF  244 Pages
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производитель  ZILOG [Zilog, Inc.]
домашняя страница  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8F082ASH020SC датащи(HTML) 33 Page - Zilog, Inc.

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PS024705-0405
P R E L I M I N A R Y
Register Map
Z8 Encore! XP® F08xA Series
Product Specification
15
Register Map
Table 7 provides the address map for the Register File of the Z8 Encore! XP® F08xA
Series devices. Not all devices and package styles in the Z8 Encore! XP® F08xA Series
support the ADC, or all of the GPIO Ports. Consider registers for unimplemented periph-
erals as Reserved.
Table 7. Register File Address Map
Address (Hex)
Register Description
Mnemonic
Reset (Hex)
Page #
General Purpose RAM
Z8F082A/Z8F081A Devices
000–3FF
General-Purpose Register File RAM
—
XX
400–EFF
Reserved
—
XX
Timer 0
F00
Timer 0 High Byte
T0H
00
72
F01
Timer 0 Low Byte
T0L
01
72
F02
Timer 0 Reload High Byte
T0RH
FF
73
F03
Timer 0 Reload Low Byte
T0RL
FF
73
F04
Timer 0 PWM High Byte
T0PWMH
00
73
F05
Timer 0 PWM Low Byte
T0PWML
00
74
F06
Timer 0 Control 0
T0CTL0
00
74
F07
Timer 0 Control 1
T0CTL1
00
75
Timer 1
F08
Timer 1 High Byte
T1H
00
72
F09
Timer 1 Low Byte
T1L
01
72
F0A
Timer 1 Reload High Byte
T1RH
FF
73
F0B
Timer 1 Reload Low Byte
T1RL
FF
73
F0C
Timer 1 PWM High Byte
T1PWMH
00
73
F0D
Timer 1 PWM Low Byte
T1PWML
00
74
F0E
Timer 1 Control 0
T1CTL0
00
74
F0F
Timer 1 Control 1
T1CTL1
00
72
F10–F3F
Reserved
—
XX
UART 0
F40
UART0 Transmit Data
U0TXD
XX
95
UART0 Receive Data
U0RXD
XX
96
XX=Undefined



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