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Z8F082ASH020SC датащи(PDF) 84 Page - Zilog, Inc. |
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Z8F082ASH020SC датащи(HTML) 84 Page - Zilog, Inc. |
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84 / 244 page ![]() PS024705-0405 P R E L I M I N A R Y Timers Z8 Encore! XP® F08xA Series Product Specification 66 6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 7. Configure the associated GPIO port pin for the Timer Output and Timer Output Complement alternate functions. The Timer Output Complement function is shared with the Timer Input function for both timers. Setting the timer mode to Dual PWM automatically switches the function from Timer In to Timer Out Complement. 8. Write to the Timer Control register to enable the timer and initiate counting. The PWM period is represented by the following equation: If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, the ONE-SHOT mode equation determines the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is repre- sented by: If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre- sented by: CAPTURE Mode In CAPTURE mode, the current timer count value is recorded when the appropriate exter- nal Timer Input transition occurs. The Capture count value is written to the Timer PWM High and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer Control register determines if the Capture occurs on a rising edge or a falling edge of the Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer continues counting. The INPCAP bit in TxCTL1 register is set to indicate the timer interrupt is because of an input capture event. The timer continues counting up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt and continues counting. The INPCAP bit in TxCTL1 register clears indicating the timer interrupt is not because of an input capture event. The steps for configuring a timer for CAPTURE mode and initiating the count are as fol- lows: PWM Period (s) Reload Value Prescale × System Clock Frequency (Hz) ---------------------------------------------------------------------------- = PWM Output High Time Ratio (%) Reload Value PWM Value – Reload Value ------------------------------------------------------------------------ 100 × = PWM Output High Time Ratio (%) PWM Value Reload Value ---------------------------------- 100 × = |
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