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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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Z8F082ASH020SC датащи(PDF) 55 Page - Zilog, Inc. |
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Z8F082ASH020SC датащи(HTML) 55 Page - Zilog, Inc. |
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55 / 244 page  PS024705-0405 P R E L I M I N A R Y General-Purpose I/O Z8 Encore! XP® F08xA Series Product Specification 37 GPIO Control Register Definitions Four registers for each Port provide access to GPIO control, input data, and output data. Table 15 lists these Port registers. Use the Port A–D Address and Control registers together to provide access to sub-registers for Port configuration and control. Port A–D Address Registers The Port A–D Address registers select the GPIO Port functionality accessible through the Port A–D Control registers. The Port A–D Address and Control registers combine to pro- vide access to all GPIO Port controls (Table 16). Table 15. GPIO Port Registers and Sub-Registers Port Register Mnemonic Port Register Name PxADDR Port A–D Address Register (Selects sub-registers) PxCTL Port A–D Control Register (Provides access to sub-registers) PxIN Port A–D Input Data Register PxOUT Port A–D Output Data Register Port Sub-Register Mnemonic Port Register Name PxDD Data Direction PxAF Alternate Function PxOC Output Control (Open-Drain) PxHDE High Drive Enable PxSMRE STOP Mode Recovery Source Enable PxPUE Pull-up Enable PxAFS1 Alternate Function Set 1 PxAFS2 Alternate Function Set 2 Table 16. Port A–D GPIO Address Registers (PxADDR) BITS 7 6 5 4 3 2 1 0 FIELD PADDR[7:0] RESET 00H R/W R/WR/W R/WR/W R/WR/W R/WR/W ADDR FD0H, FD4H, FD8H, FDCH |
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