MPC885ZP80 datasheet(11/87 Pages) NXP

11 / 87 page

MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7

Freescale Semiconductor

Power Dissipation

Table 5 provides information on power dissipation. The modes are 1:1, where CPU and bus speeds are

equal, and 2:1, where CPU frequency is twice bus speed.

NOTE

The values in Table 5 represent VDDL-based power dissipation and do not

include I/O power dissipation over VDDH. I/O power dissipation varies

widely by application due to buffer current, depending on external circuitry.

The VDDSYN power dissipation is negligible.

DC Characteristics

Table 6 provides the DC electrical characteristics for the MPC885/MPC880.

Table 5. Power Dissipation (PD)

Die Revision

Bus Mode

CPU

Frequency

Typical1

1 Typical power dissipation at V

DDL = VDDSYN = 1.8 V, and VDDH is at 3.3 V.

Maximum2

2 Maximum power dissipation at V

DDL = VDDSYN = 1.9 V, and VDDH is at 3.5 V.

Unit

1:1

66 MHz

310

390

80 MHz

350

430

2:1

133 MHz

430

495

Table 6. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Operating voltage

VDDL (core)

1.7

1.9

VDDH (I/O)

3.135

3.465

VDDSYN

1.7

1.9

Difference

between VDDL

and VDDSYN

—100

Input high voltage (all inputs except EXTAL and EXTCLK)2

VIH

2.0

3.465

Input low voltage3

VIL

GND

0.8

EXTAL, EXTCLK input high voltage

VIHC

0.7*(VDDH)VDDH

Input leakage current, Vin = 5.5 V (except TMS, TRST, DSCK and DSDI

pins) for 5-V tolerant pins 2

Iin

—

100

µA

Input leakage current, Vin = VDDH (except TMS, TRST, DSCK, and DSDI)

IIn

—10

µA

Input leakage current, Vin = 0 V (except TMS, TRST, DSCK and DSDI

pins)

IIn

—10

µA

Input capacitance4

Cin

—20

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