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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC885ZP80 датащи(PDF) 73 Page - NXP Semiconductors |
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MPC885ZP80 датащи(HTML) 73 Page - NXP Semiconductors |
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73 / 87 page  MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 73 FEC Electrical Characteristics Figure 74 shows the MII transmit signal timing diagram. Figure 74. MII Transmit Signal Timing Diagram 15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL) Table 36 provides information on the MII async inputs signal timing. Figure 75 shows the MII asynchronous inputs signal timing diagram. Figure 75. MII Async Inputs Timing Diagram 15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Table 37 provides information on the MII serial management channel signal timing. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. Table 36. MII Async Inputs Signal Timing Num Characteristic Min Max Unit M9 MII_CRS, MII_COL minimum pulse width 1.5 — MII_TX_CLK period Table 37. MII Serial Management Channel Timing Num Characteristic Min Max Unit M10 MII_MDC falling edge to MII_MDIO output invalid (minimum propagation delay) 0— ns M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay) — 25 ns M12 MII_MDIO (input) to MII_MDC rising edge setup 10 — ns M13 MII_MDIO (input) to MII_MDC rising edge hold 0 — ns M6 MII_TX_CLK (Input) MII_TXD[3:0] (Outputs) MII_TX_EN MII_TX_ER M5 M7 M8 RMII_REFCLK MII_CRS, MII_COL M9 |
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