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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC885ZP80 датащи(PDF) 63 Page - NXP Semiconductors |
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MPC885ZP80 датащи(HTML) 63 Page - NXP Semiconductors |
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63 / 87 page  MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 63 CPM Electrical Characteristics Figure 64. Ethernet Transmit Timing Diagram 12.9 SMC Transparent AC Electrical Specifications Table 25 provides the SMC transparent timings as shown in Figure 65. Table 25. SMC Transparent Timing Num Characteristic All Frequencies Unit Min Max 150 SMCLK clock period1 1 SyncCLK must be at least twice as fast as SMCLK. 100 — ns 151 SMCLK width low 50 — ns 151A SMCLK width high 50 — ns 152 SMCLK rise/fall time — 15 ns 153 SMTXD active delay (from SMCLK falling edge) 10 50 ns 154 SMRXD/SMSYNC setup time 20 — ns 155 RXD1/SMSYNC hold time 5 — ns TCLK1 128 TxD1 (Output) 128 TENA(RTS1) (Input) Notes: Transmit clock invert (TCI) bit in GSMR is set. If RENA is negated before TENA or RENA is not asserted at all during transmit, then the CSL bit is set in the buffer descriptor at the end of the frame transmission. 1. 2. RENA(CD1) (Input) 133 134 132 131 121 129 (Note 2) |
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