MPC885ZP80 datasheet(16/87 Pages) NXP

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MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7

Freescale Semiconductor

Layout Practices

Figure 5. Example Voltage Sequencing Circuit

Layout Practices

Each VDD pin on the MPC885/MPC880 should be provided with a low-impedance path to the board’s

supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power

supply pins drive distinct groups of logic on chip. The VDD power supply should be bypassed to ground

using at least four 0.1 µF by-pass capacitors located as close as possible to the four sides of the package.

Each board designed should be characterized and additional appropriate decoupling capacitors should be

used if required. The capacitor leads and associated printed-circuit traces connecting to chip VDD and

GND should be kept to less than half an inch per capacitor lead. At a minimum, a four-layer board

employing two inner layers as VDD and GND planes should be used.

All output pins on the MPC885/MPC880 have fast rise and fall times. Printed-circuit (PC) trace

interconnection length should be minimized in order to minimize undershoot and reflections caused by

these fast output switching times. This recommendation particularly applies to the address and data buses.

Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all

device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and

bypassing becomes especially critical in systems with higher capacitive loads because these loads create

higher transient currents in the VDD and GND circuits. Pull up all unused inputs or signals that will be

inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. For

more information, please refer to the MPC885 PowerQUICC™ Family Reference Manual, Section 14.4.3,

“Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1).”

10 Bus Signal Timing

The maximum bus speed supported by the MPC885/MPC880 is 80 MHz. Higher-speed parts must be

operated in half-speed bus mode (for example, an MPC885/MPC880 used at 133 MHz must be configured

for a 66 MHz bus). Table 7 shows the frequency ranges for standard part frequencies in 1:1 bus mode, and

Table 8 shows the frequency ranges for standard part frequencies in 2:1 bus mode.

VDDH

VDDL

1N5820

MUR420

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