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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC885ZP80 датащи(PDF) 42 Page - NXP Semiconductors |
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MPC885ZP80 датащи(HTML) 42 Page - NXP Semiconductors |
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42 / 87 page  MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 42 Freescale Semiconductor Bus Signal Timing Table 14 shows the reset timing for the MPC885/MPC880. Table 14. Reset Timing Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit Min Max Min Max Min Max Min Max R69 CLKOUT to HRESET high impedance (MAX = 0.00 × B1 + 20.00) — 20.00 — 20.00 — 20.00 — 20.00 ns R70 CLKOUT to SRESET high impedance (MAX = 0.00 × B1 + 20.00) — 20.00 — 20.00 — 20.00 — 20.00 ns R71 RSTCONF pulse width (MIN = 17.00 × B1) 515.20 — 425.00 — 257.60 — 212.50 — ns R72 — —— —— —— —— — R73 Configuration data to HRESET rising edge setup time (MIN = 15.00 × B1 + 50.00) 504.50 — 425.00 — 277.30 — 237.50 — ns R74 Configuration data to RSTCONF rising edge setup time (MIN = 0.00 × B1 + 350.00) 350.00 — 350.00 — 350.00 — 350.00 — ns R75 Configuration data hold time after RSTCONF negation (MIN = 0.00 × B1 + 0.00) 0.00 — 0.00 — 0.00 — 0.00 — ns R76 Configuration data hold time after HRESET negation (MIN = 0.00 × B1 + 0.00) 0.00 — 0.00 — 0.00 — 0.00 — ns R77 HRESET and RSTCONF asserted to data out drive (MAX = 0.00 × B1 + 25.00) — 25.00 — 25.00 — 25.00 — 25.00 ns R78 RSTCONF negated to data out high impedance (MAX = 0.00 × B1 + 25.00) — 25.00 — 25.00 — 25.00 — 25.00 ns R79 CLKOUT of last rising edge before chip three-states HRESET to data out high impedance (MAX = 0.00 × B1 + 25.00) — 25.00 — 25.00 — 25.00 — 25.00 ns R80 DSDI, DSCK setup (MIN = 3.00 × B1) 90.90 — 75.00 — 45.50 — 37.50 — ns R81 DSDI, DSCK hold time (MIN = 0.00 × B1 + 0.00) 0.00 — 0.00 — 0.00 — 0.00 — ns R82 SRESET negated to CLKOUT rising edge for DSDI and DSCK sample (MIN = 8.00 × B1) 242.40 — 200.00 — 121.20 — 100.00 — ns |
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