MPC885ZP80 datasheet(3/87 Pages) NXP

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MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7

Freescale Semiconductor

Features

•

Provides enhanced ATM functionality found on the MPC862 and MPC866 families and includes

the following:

— Improved operation, administration and maintenance (OAM) support

— OAM performance monitoring (PM) support

— Multiple APC priority levels available to support a range of traffic pace requirements

— Port-to-port switching capability without the need for RAM-based microcode

— Simultaneous MII (100BaseT) and UTOPIA (half- or full -duplex) capability

— Optional statistical cell counters per PHY

— UTOPIA L2-compliant interface with added FIFO buffering to reduce the total cell

transmission time and multi-PHY support. (The earlier UTOPIA L1 specification is also

supported.)

— Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode

— Supports full-duplex UTOPIA master (ATM side) and slave (PHY side) operations using a split

bus

— AAL2/VBR functionality is ROM-resident

•

Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

•

Thirty-two address lines

•

Memory controller (eight banks)

— Contains complete dynamic RAM (DRAM) controller

— Each bank can be a chip select or RAS to support a DRAM bank

— Up to 30 wait states programmable per memory bank

— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory

devices

— DRAM controller programmable to support most size and speed memory interfaces

— Four CAS lines, four WE lines, and one OE line

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbytes–256 Mbytes)

— Selectable write protection

— On-chip bus arbitration logic

•

General-purpose timers

— Four 16-bit timers or two 32-bit timers

— Gate mode can enable/disable counting.

— Interrupt can be masked on reference match and event capture

•

Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE Std. 802.3™ CDMA/CS

that interface through MII and/or RMII interfaces

•

System integration unit (SIU)

— Bus monitor

— Software watchdog

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