MPC885ZP80 datasheet(5/87 Pages) NXP

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MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7

Freescale Semiconductor

Features

•

On-chip 16

× 16 multiply accumulate controller (MAC)

— One operation per clock (two-clock latency, one-clock blockage)

— MAC operates concurrently with other instructions

— FIR loop—Four clocks per four multiplies

•

Four baud rate generators

— Independent (can be connected to any SCC or SMC)

— Allow changes during operation

— Autobaud support option

•

Up to three serial communication controllers (SCCs) supporting the following protocols:

— Serial ATM capability on SCCs

— Optional UTOPIA port on SCC4

— Ethernet/IEEE Std 802.3™ optional on the SCC(s) supporting full 10-Mbps operation

— HDLC/SDLC

— HDLC bus (implements an HDLC-based local area network (LAN))

— Asynchronous HDLC to support point-to-point protocol (PPP)

— AppleTalk

— Universal asynchronous receiver transmitter (UART)

— Synchronous UART

— Serial infrared (IrDA)

— Binary synchronous communication (BISYNC)

— Totally transparent (bit streams)

— Totally transparent (frame based with optional cyclic redundancy check (CRC))

•

Up to two serial management channels (SMCs) supporting the following protocols:

— UART (low-speed operation)

— Transparent

— General circuit interface (GCI) controller

— Provide management for BRI devices as GCI controller in time-division multiplexed (TDM)

channels

•

Universal serial bus (USB)—Supports operation as a USB function endpoint, a USB host

controller, or both for testing purposes (loop-back diagnostics)

— USB 2.0 full-/low-speed compatible

— The USB function mode has the following features:

– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers.

– CRC16 generation and checking

– CRC5 checking

– NRZI encoding/decoding with bit stuffing

– 12- or 1.5-Mbps data rate

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