ADPD107 datasheet(29/66 Pages) AD

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Data Sheet

ADPD105/ADPD106/ADPD107

Rev. A | Page 29 of 66

A sample timing diagram for a multiple word SPI write operation

to a register is shown in Figure 31. A sample timing diagram of

a single-word SPI read operation is shown in Figure 32. The

MISO pin transitions from being three-state to being driven

following the reception of a valid R bit. In this example, Byte 0

contains the address and the W/R bit, and subsequent bytes

carry the data. A sample timing diagram of a multiple word SPI

read operation is shown in Figure 33. In Figure 31 to Figure 33,

rising edges on SCLK are indicated with an arrow, signifying

that the data lines are sampled on the rising edge.

When performing multiple word reads or writes, the data

address is automatically incremented to the next consecutive

address for subsequent transactions except for Address 0x5F,

Address 0x60 (FIFO), and Address 0x7F.

123

4567

89 10 11 12 13 14 15 16 17 18 19 20 21 22

SCLK

MOSI

DATA BYTE 1

DATA BYTE 2

DATA BYTE N

ADDRESS[6:0]

W/R

Figure 31. SPI Slave Write Clocking (Burst Write Mode, N Bytes)

0123

4567

89 10 11 12 13 14 15 16 17 18 19 20 21 22

SCLK

MOSI

MISO

DATA BYTE 1

DATA BYTE 2

ADDRESS[6:0]

W/R

Figure 32. SPI Slave Read Clocking (Single-Word Mode, Two Bytes)

01234 56789 10 11 12 13 14 15 16 17 18 19 20 21 22

SCLK

MOSI

MISO

DATA BYTE 1

DATA BYTE 2

DATA BYTE N

ADDRESS[6:0]

W/R

Figure 33. SPI Slave Read Clocking (Burst Read Mode, N Bytes)

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