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ADPD105/ADPD106/ADPD107

Data Sheet

Rev. A | Page 42 of 66

Table 26. Analog Specifications for TIA ADC and Digital Integrate Modes

Parameter

Test Conditions/Comments

Typ

Unit

TIA ADC/Digital Integration Saturation Levels

Values expressed per channel, per sample; TIA feedback resistor

25 kΩ

38.32

μA

50 kΩ

19.16

μA

100 kΩ

9.58

μA

200 kΩ

4.79

μA

TIA ADC Resolution

Values expressed per channel, per sample; TIA feedback resistor

25 kΩ

2.92

nA/LSB

50 kΩ

1.5

nA/LSB

100 kΩ

0.73

nA/LSB

200 kΩ

0.37

nA/LSB

Output with No Input Photocurrent

ADC offset (Register 0x18 to Register 0x21) = 0x0

13,000

LSB

DIGITAL INTEGRATE MODE

Digital integrate mode is built into the ADPD105/ADPD106/

ADPD107 and allows the device to accommodate longer

LED/AFE pulse widths and different types of sensors at the

input. The analog integration mode described in the AFE

Operation section is ideally suited for applications requiring a

large LED duty cycle, or applications that require customization

of the sampling scheme. Digital integrate mode allows the

integration function to be performed after the ADC in the

digital domain. This mode enables the device to handle a much

wider range of sensors at the input.

In digital integrate mode, the ADC performs a conversion every

1 μs during the integration window. During the integration

window, the digital engine either adds to or subtracts from

the previous sample. The band-pass filter is bypassed and the

integrator is converted to a voltage buffer, allowing the digital

engine to perform the integration function. In this mode, after

the timing is optimized, the output of the ADC increases as the

light level on the photodiode increases.

The integration window is a combination of negative and positive

windows where the duration of these windows is set by SLOTx_

AFE_WIDTH. At the end of the digital integration window, the

resulting sum is sent to the decimate unit as the sample for that

LED pulse. There is one sample per time slot for every sample

cycle. Table 27 lists the registers required for placing the device

in digital integrate mode.

There may also be changes needed in the SLOTx_AFE_OFFSET

registers and FIFO configuration register (0x11). To read the

final value through the FIFO, set the appropriate values in Regis-

ter 0x11, Bits[4:2] for Time Slot A, and Register 0x11, Bits[8:6]

for Time Slot B. Alternatively, the final output is also available

through the data registers; Register 0x64, Register 0x70, and

and Register 0x7C for Time Slot B.

To put the ADPD105/ADPD106/ADPD107 into digital

integration mode during Time Slot A, write 0x1 to Register 0x58,

Bit 12. To put the ADPD105/ADPD106/ADPD107 into digital

integration mode in Time Slot B, write 0x1 to Register 0x58, Bit 13.

The other writes required to switch to digital integration mode

are listed in Table 27.

When using digital integrate mode, up to two photodiodes can

be connected to the ADPD105/ADPD106/ADPD107 inputs; one

photodiode per PDx input group (PD1/PD2/PD3/PD4 or PD5/

PD6/PD7/PD8). Never connect the same photodiode across the

two PDx groups. In digital integrate mode, there are options to

connect the photodiode to all four AFE channels (PD1/PD2/PD3/

PD4 or PD5/PD6/PD7/PD8), or just a single AFE channel (PD1

or PD5). When connecting to a single AFE channel, write 0x1

to Register 0x54, Bit 14 for Time Slot A, or, for Time Slot B,

write 0x1 to Register 0x54, Bit 15.

When connecting to a single AFE channel, there is also an

option to turn off Channel 2, Channel 3, and Channel 4 (and to

save power) by writing 0x7 to Register 0x55, Bits[15:13]. When

connecting to all four channels (PD1/PD2/PD3/PD4 or PD5/

PD6/PD7/PD8), write 0x0 (default)to Register 0x54, Bit 14 for

Time Slot A, or write 0x0 (default) to Register 0x54, Bit 15 for

Time Slot B. Ensure that all AFE channels are powered up by

writing 0x0 to Register 0x55, Bits[15:13].

Connecting the single photodiode to a single AFE channel offers

the best SNR performance in cases where signal is limited, whereas

connecting the single photodiode to all four AFE channels offers

the best dynamic range in cases where signal is large.

Digital Integration Sampling Modes

There are two sampling modes that can be used while the

device is in digital integration mode. These modes are single-

sample pair mode and double-sample pair mode.

In single-sample pair mode, there is a single negative sample

region and a single positive sample region, shown in Figure 48

and Figure 49. To use single-sample pair mode, write 0x1 to

Time Slot B. The negative sample region starts at SLOTx_AFE_

OFFSET + 9 and its duration (the number of samples taken) is set

by SLOTx_AFE_WIDTH. The positive sample region starts at

SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_WIDTH, and its

duration is also set by SLOTx_AFE_WIDTH. Set the timing

such that the negative sample region falls entirely in the flat

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