ADPD107 datasheet(28/66 Pages) AD

28 / 66 page

ADPD105/ADPD106/ADPD107

Data Sheet

Rev. A | Page 28 of 66

NOTES

1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.

MASTER START

SLAVE ADDRESS + WRITE

SLAVE

ACK

MASTER START

SLAVE ADDRESS + WRITE

ACK/NACK

STOP

SLAVE

ACK

DATA[7:0]

DATA[15:8]

SLAVE ADDRESS + READ

ACK

DATA[7:0]

DATA[15:8]

STOP

ACK

DATA TRANSFERRED

n (DATA[15:8]+ACK+DATA[7:0] + ACK/NACK)

MASTER START

SLAVE ADDRESS + WRITE

NACK

STOP

SLAVE

ACK

DATA[7:0]

SLAVE ADDRESS + READ

ACK

DATA[15:8]

ACK

I2C WRITE

I2C SINGLE WORD READ MODE

I2C MULTIWORD READ MODE

Figure 29. I2C Write and Read Operations

SPI PORT

The ADPD106 and ADPD107 are SPI only devices. They do not

support the I2C interface. The SPI port uses a 4-wire interface,

consisting of the CS, MOSI, MISO, and SCLK signals, and it is

always a slave port. The CS signal goes low at the beginning of a

transaction and high at the end of a transaction. The SCLK signal

latches MOSI on a low to high transition. The MISO data is shifted

out of the device on the falling edge of SCLK and must be clocked

into a receiving device, such as a microcontroller, on the SCLK

rising edge. The MOSI signal carries the serial input data, and

the MISO signal carries the serial output data. The MISO signal

remains three state until a read operation is requested, which

allows other SPI-compatible peripherals to share the same MISO

line. All SPI transactions have the same basic format shown in

Table 20. A timing diagram is shown in Figure 4. Write all data

MSB first.

Table 20. Generic Control Word Sequence

Byte 0

Byte 1

Byte 2

Subsequent Bytes

Address[6:0],

W/R

Data[15:8]

Data[7:0]

Data[15:8], Data[7:0]

The first byte written in a SPI transaction is a 7-bit address,

which is the location of the address being accessed, followed by

the W/R bit. This bit determines whether the communication is

a write (Logic Level 1) or a read (Logic Level 0). This format is

shown in Table 21.

Table 21. SPI Address and Write/R Byte Format

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

W/R

The format for the SPI communications slave port is commonly

known as SPI Mode 3, where clock polarity (CPOL) = 1 and

clock phase (CPHA) = 1 (see Figure 30). The base value of the

clock is 1. Data is captured on the rising edge of the clock, and

data is propagated on the falling edge.

The maximum read and write speed for the SPI slave port is

10 MHz.

(CPOL = 1)

SCLK

(CPHA = 1)

MISO

CYCLE #

MOSI

Figure 30. Clock Polarity and Phase for the SPI Slave Port (CPOL = 1, CPHA = 1)

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