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ADPD105/ADPD106/ADPD107

Data Sheet

Rev. A | Page 22 of 66

Table 17. Time Slot Switch (Register 0x14)

Address

Bits

Name

Description

0x14

[11:8]

SLOTB_PD_SEL

Selects connection of photodiode for Time Slot B as shown in Figure 22 and Figure 23.

0x0: inputs are floating in Time Slot B.

0x1: PD1-2 is connected to Channel 1; PD3-4 is connected to Channel 2 during Time Slot B.

0x5: PD1-2 is connected to Channel 1 and Channel 2; PD3-4 is connected to Channel 3

and Channel 4 during Time Slot B.

Other: reserved.

[7:4]

SLOTA_PD_SEL

Selects connection of photodiode for Time Slot A as shown in Figure 22 and Figure 23.

0x0: inputs are floating in Time Slot A.

0x1: PD1-2 is connected to Channel 1; PD3-4 is connected to Channel 2 during Time Slot A.

0x5: PD1-2 is connected to Channel 1 and Channel 2; PD3-4 is connected to Channel 3

and Channel 4 during Time Slot A.

Other: reserved.

ADJUSTABLE SAMPLING FREQUENCY

ADPD105/ADPD106/ADPD107 and Register 0x4B, Bits[5:0]

further tunes this clock for greater accuracy. The sampling

frequency is governed by an internal 32 kHz sample rate clock

that also drives the trans-ition of the internal state machine. The

maximum sampling frequencies for some sample conditions

are listed in Table 3. The maximum sample frequency for all

conditions is determined by the following equation:

fSAMPLE, MAX = 1/(tA + t1 + tB + t2 + tSLEEP, MIN)

where tSLEEP, MIN is the minimum sleep time required between

samples.

If a given time slot is not in use, elements from that time slot do

not factor into the calculation. For example, if Time Slot A is

not in use, tA and t1 do not add to the sampling period and the

new maximum sampling frequency is calculated as follows:

fSAMPLE, MAX = 1/(tB + t2 + tSLEEP, MIN)

See the Dual Time Slot Operation section for the definitions of

tA, t1, tB, and t2.

External Sync for Sampling

The ADPD105/ADPD106/ADPD107 provide an option to use

an external sync signal to trigger the sampling periods. This

external sample sync signal can be provided either on the

GPIO0 pin or the GPIO1 pin. This functionality is controlled

by Register 0x4F, Bits[3:2]. When enabled, a rising edge on

the selected input specifies when the next sample cycle occurs.

When triggered, there is a delay of one to two internal sampling

clock (32 kHz) cycles, and then the normal start-up sequence

occurs. This sequence is the same as when the normal sample

timer providesthe trigger. To enable the external sync signal

feature, use the following procedure:

Write 0x1 to Register 0x10 to enter program mode.

Write the appropriate value to Register 0x4F, Bits[3:2] to

select whether the GPIO0 pin or the GPIO1 pin specifies

when the next sample cycle occurs. Also, enable the

appropriate input buffer using Register 0x4F, Bit 1, for the

GPIO0 pin, or Register 0x4F, Bit 5, for the GPIO1 pin.

Write 0x4000 to Register 0x38.

Write 0x2 to Register 0x10 to start the sampling operations.

Apply the external sync signal on the selected pin at the

desired rate; sampling occurs at that rate. As with normal

sampling operations, read the data using the FIFO or the

data registers.

The maximum frequency constraints also apply in this case.

Providing an External 32kHz Clock

The ADPD105/ADPD106/ADPD107 have an option for the

user to provide an external 32 kHz clock to the devices for

system synchronization or for situations where a clock with

better accuracy than the internal 32 kHz clock is required. The

external 32 kHz clock is provided on the GPIO1 pin. To enable

the 32 kHz external clock, use the following procedure at startup:

Drive the GPIO1 pin to a valid logic level or with the

desired 32 kHz clock prior to enabling the GPIO1 pin as an

input. Do not leave the pin floating prior to enabling it.

Write 01 to Register 0x4F, Bits[6:5] to enable the GPIO1 pin as

an input.

Write 10 to Register 0x4B, Bits[8:7] to configure the devices to

use an external 32 kHz clock. This setting disables the

internal 32 kHz clock and enables the external 32 kHz clock.

Write 0x1 to Register 0x10 to enter program mode.

Write additional control registers in any order while the

devices are in program mode to configure the devices as

required.

Write 0x2 to Register 0x10 to start the normal sampling

operation.

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