ADPD107 datasheet(34/66 Pages) AD

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ADPD105/ADPD106/ADPD107

Data Sheet

Rev. A | Page 34 of 66

Enter normal operation mode by setting Register 0x10 to 0x2.

When an interrupt occurs

a. There is no requirement to read the FIFO_SAMPLES bits,

because the interrupt is generated only if there is one or

more full packets. Optionally, the interrupt routine can

check for the presence of more than one available

packet by reading these bits.

b. Read a complete packet using one or more multiword

accesses using Register 0x60. Reading the FIFO

automatically frees the space for new samples.

The FIFO interrupt automatically clears immediately upon

reading any data from the FIFO and is set again only when the

FIFO is written and the number of words is above the threshold.

Polling Method

To read data from the FIFO in a polling method, use the

following procedure:

In program mode, set the configuration of the time slots as

desired for operation.

Write Register 0x11 with the desired data format for each

time slot.

Enter normal operation mode by setting Register 0x10 to 2.

Next, begin the polling operations.

Wait for the polling interval to expire.

Read the FIFO_SAMPLES bits (Register 0x00, Bits[15:8]).

If FIFO_SAMPLES ≥ the packet size, read a packet using

the following steps:

a. Read a complete packet using one or more multiword

accesses via Register 0x60. Reading the FIFO

automatically frees the space for new samples.

b. Repeat Step 1.

When a mode change is required, or any other disruption to

normal sampling is necessary, the FIFO must be cleared. Use

the following procedure to clear the state and empty the FIFO:

Enter program mode by setting Register 0x10 to 0x1.

Write 1 to Register 0x00, Bit 15.

Reading Data from Registers Using Interrupts

The latest sample data is always available in the data registers and is

updated simultaneously at the end of each time slot. The data value

for each photodiode channel is available as a 16-bit value in Regis-

ter 0x64 through Register 0x67 for Time Slot A, and Register 0x68

through Register 0x6B for Time Slot B. If allowed to reach their

maximum value, Register 0x64 through Register 0x6B clip. If

to 27 bits) values for each channel are available in Register 0x70

through Register 0x77 for Time Slot A and Register 0x78 through

indicate when the registers are updated and can be read. To use

the interrupt for a given time slot, use the following procedure:

Enable the sample interrupt by writing a 0 to the appropriate

bit in Register 0x01. To enable the interrupt for Time Slot A,

write 0 to Bit 5. To enable the interrupt for Time Slot B,

write 0 to Bit 6. Either or both interrupts can be set.

Configure the interrupt pin (GPIOx) by writing the

appropriate value to the bits in Register 0x02.

An interrupt generates when the data registers are updated.

The interrupt handler must perform the following:

a. Read Register 0x00 and observe Bit 5 or Bit 6 to confirm

which interrupt has occurred. This step is not required if

only one interrupt is in use.

b. Read the data registers before the next sample can be

written. The system must have interrupt latency and

service time short enough to respond before the next

data update, based on the output data rate.

c. Write a 1 to Bit 5 or Bit 6 in Register 0x00 to clear the

interrupt.

If both time slots are in use, it is possible to use only the

Time Slot B interrupt to signal when all registers can be read. It

is recommended to use the multiword read to transfer the data

from the data registers.

Reading Data from Registers Without Interrupts

If the system interrupt response is not fast or predictable enough to

use the interrupt method, or if the interrupt pin (GPIOx) is not

used, it is possible to obtain reliable data access by using the data

hold mechanism. To guarantee that the data read from the registers

is from the same sample time, it is necessary to prevent the

update of samples while reading the current values. The method

for doing register reads without interrupt timing is as follows:

Write a 1 to SLOTA_DATA_HOLD or SLOTB_DATA_

HOLD (Register 0x5F, Bit 1 and Bit 2, respectively) for the

time slot requiring access (both time slots can be accessed).

This setting prevents sample updates.

Read the registers as desired.

Write a 0 to the SLOTA_DATA_HOLD or SLOTB_DATA_

HOLD bits (Register 0x5F, Bit 1 and Bit 2, respectively)

previously set. Sample updates are allowed again.

Because a new sample may arrive while the reads are occurring,

this method prevents the new sample from partially overwriting

the data being read.

CLOCKS AND TIMING CALIBRATION

The ADPD105/ADPD106/ADPD107 operate using two internal

time bases: a 32 kHz clock sets the sample timing, and a 32 MHz

clock controls the timing of the internal functions such as LED

pulsing and data capture. Both clocks are internally generated

and exhibit device to device variation of approximately 10%

(typical).

Heart rate monitoring applications require an accurate time

base to achieve an accurate count of beats per minute. The

ADPD105/ADPD106/ADPD107 provide a simple calibration

procedure for both clocks.

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