ADPD107 datasheet(63/66 Pages) AD

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Data Sheet

ADPD105/ADPD106/ADPD107

Rev. A | Page 63 of 66

Address

Data

Bit

Default

Access

Name

Description

0x5F

[15:3]

0x0000

R/W

Reserved

Write 0x0000.

0x0

R/W

SLOTB_DATA_HOLD

Setting this bit prevents the update of the data registers corresponding to

Time Slot B. Set this bit to ensure that unread data registers are not

updated, guaranteeing a contiguous set of data from all four photodiode

channels.

1: hold data registers for Time Slot B.

0: allow data register update.

0x0

R/W

SLOTA_DATA_HOLD

Setting this bit prevents the update of the data registers corresponding to

Time Slot A. Set this bit to ensure that unread data registers are not

updated, guaranteeing a contiguous set of data from all four photodiode

channels.

1: hold data registers for Time Slot A.

0: allow data register update.

0x0

R/W

DIGITAL_CLOCK_ENA

Set to 1 in order to enable the 32 MHz clock when calibrating the 32 MHz

clock. Always disable the 32 MHz clock following the calibration by

resetting this bit to 0.

1 Clock speed setting is only relevant during digital integrate mode.

ADC REGISTERS

Table 34. ADC Registers

Address

Data

Bits

Default

Access

Name

Description

0x12

[15:0]

0x0028

R/W

FSAMPLE

Sampling frequency: fSAMPLE = 32 kHz/(Register 0x12, Bits[15:0] × 4).

For example, 100 Hz = 0x0050; 200 Hz = 0x0028.

0x15

[15:11]

0x00

R/W

Reserved

Write 0x0.

[10:8]

0x6

R/W

SLOTB_NUM_AVG

Sample sum/average for Time Slot B. Specifies the averaging factor, NB,

which is the number of consecutive samples that is summed and averaged

after the ADC. Register 0x70 to Register 0x7F hold the data sum. Register 0x64

to Register 0x6B and the data buffer in Register 0x60 hold the data average,

which can be used to increase SNR without clipping, in 16-bit registers.

The data rate is decimated by the value of the SLOTB_NUMB_AVG bits.

0: 1.

1: 2.

2: 4.

3: 8.

4: 16.

5: 32.

6: 64.

7: 128.

0x0

R/W

Reserved

Write 0x0.

[6:4]

0x0

R/W

SLOTA_NUM_AVG

Sample sum/average for Time Slot A. NA: same as Bits[10:8] but for

Time Slot A. See description in Register 0x15, Bits[10:8].

[3:0]

0x0

R/W

Reserved

Write 0x0.

0x18

[15:0]

0x2000

R/W

SLOTA_CH1_OFFSET

Time Slot A Channel 1 ADC offset. The value to subtract from the raw ADC

value. A value of 0x2000 is typical.

0x19

[15:0]

0x2000

R/W

SLOTA_CH2_OFFSET

Time Slot A Channel 2 ADC offset. The value to subtract from the raw ADC

value. A value of 0x2000 is typical.

0x1A

[15:0]

0x2000

R/W

SLOTA_CH3_OFFSET

Time Slot A Channel 3 ADC offset. The value to subtract from the raw ADC

value. A value of 0x2000 is typical.

0x1B

[15:0]

0x2000

R/W

SLOTA_CH4_OFFSET

Time Slot A Channel 4 ADC offset. The value to subtract from the raw ADC

value. A value of 0x2000 is typical.

0x1E

[15:0]

0x2000

R/W

SLOTB_CH1_OFFSET

Time Slot B Channel 1 ADC offset. The value to subtract from the raw ADC

value. A value of 0x2000 is typical.

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