ADPD107 datasheet(38/66 Pages) AD

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ADPD105/ADPD106/ADPD107

Data Sheet

Rev. A | Page 38 of 66

Note that if either Time Slot A or Time Slot B are disabled, IAFE_x = 0

for that respective time slot. Additionally, if operating in digital

integrate mode, power savings can be realized by setting

band-pass filters that are bypassed in digital integrate mode,

changing the AFE power contribution calculation to

IAFE_x (mA) = 3.0 × 10−3 + (1.0 × 10−3 × NUM_CHANNELS) +

(5.7 × 10−3/SCALE_X × ILEDX_PK)

(8)

Average VLEDA Supply Current

To calculate the average VLEDA supply current, use Equation 9.

ILED_AVG_A = SLOTA_LED_WIDTH × ILEDA_PK × DR ×

PULSE_COUNT

(9)

where:

SLOTA_LED_WIDTH is the LED pulse width expressed in

seconds.

ILEDA_PK is the peak current, expressed in amps, for whichever

LED is selected for Time Slot A.

Average VLEDB Supply Current

To calculate the average VLEDB supply current, use Equation 10.

ILED_AVG_B = SLOTB_LED_WIDTH × ILEDB_PK × DR ×

PULSE_COUNT

(10)

where:

SLOTB_LED_WIDTH is the LED pulse width expressed in

seconds.

ILEDB_PK is the peak current, expressed in amps, for whichever

LED is selected for Time Slot B.

OPTIMIZING SNR PER WATT

The ADPD105/ADPD106/ADPD107 offer a variety of

parameters that the user can adjust to achieve the best signal.

One of the key goals of system performance is to obtain the best

system SNR for the lowest total power. This goal is often referred

to as optimizing SNR/watt. Even in systems where only the SNR

matters and power is a secondary concern, there may be a lower

power or a high power means of achieving the same SNR.

Optimizing for Peak SNR

The first step in optimizing for peak SNR is to find a TIA gain

and LED level that gives the best performance where the

number of LED pulses remains constant. If peak SNR is the

goal, the noise section of Table 4 can be used as a guide. It is

important to note that the SNR improves as a square root of the

number of pulses averaged together, whereas the increase in the

LED power consumed is directly proportional to the number of

LED pulses. In other words, for every doubling of the LED pulse

count, there is a doubling of the LED power consumed and a 3 dB

SNR improvement. As a result, avoid any change in the gain con-

figuration that provides less than 3 dB of improvement for a 2×

power penalty; any TIA gain configuration that provides more

than 3 dB of improvement for a 2× power penalty is a good

choice. If peak SNR is the goal and there is no issue saturating

the photodiode with LED current at any gain, the 50k TIA gain

setting is an optimal choice. After the SNR per pulse per channel is

optimized, the user can then increase the number of pulses to

achieve the desired system SNR.

Optimizing SNR per Watt in a Signal Limited System

In practice, optimizing for peak SNR is not always practical.

One scenario in which the PPG signal has a poor SNR is the

signal limited regime. In this scenario, the LED current reaches

an upper limit before the desired dc return level is achieved.

Tuning in this case starts where the peak SNR tuning stops. The

starting point is nominally a 50k gain, as long as the lowest LED

current setting of 8 mA does not saturate the photodiode and the

50k gain provides enough protection against intense background

light. In these cases, use a 25k gain as the starting point.

The goal of the tuning process is to bring the dc return signal to a

specific ADC range, such as 50% or 60%. The ADC range choice is

a function of the margin of headroom needed to prevent saturation

as the dc level fluctuates over time. The SNR of the PPG waveform

is always some percentage of the dc level. If the target level cannot

be achieved at the base gain, increase the gain and repeat the

procedure. The tuning system may need to place an upper limit

on the gain to prevent saturation from ambient signals.

Tuning the Pulse Count

After the LED peak current and TIA gain are optimized,

increasing the number of pulses per sample increases the SNR

by the square root of the number of pulses. There are two ways to

increase the pulse count. The pulse count registers (Register 0x31,

Bits[15:8], and Register 0x36, Bits[15:8]) change the number of

pulses per internal sample. Register 0x15, Bits[6:4] and Bits[10:8],

controls the number of internal samples that are averaged together

before the data is sent to the output. Therefore, the number of

pulses per sample is the pulse count register multiplied by the

number of subsequent samples being averaged. In general, the

internal sampling rate increases as the number of internal

sample averages increase to maintain the desired output data

rate. The SNR/watt is most optimal with pulse count values of

16 or less. Above pulse count values of 16, the square root

relationship does not hold in the pulse count register. However,

this relationship continues to hold when averaged between

samples using Register 0x15.

Note that increasing LED peak current increases SNR almost

directly proportional to LED power, whereas increasing the

number of pulses by a factor of n results in only a nominal√(n)

increase in SNR.

When using the sample sum/average function (Register 0x15),

the output data rate decreases by the number of summed

samples. To maintain a static output data rate, increase the

sample frequency (Register 0x12) by the same factor as that

selected in Register 0x15. For example, for a 100 Hz output data

rate and a sample sum/average of four samples, set the sample

frequency to 400 Hz.

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