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ADPD107 датащи(PDF) 55 Page - Analog Devices

номер детали ADPD107
подробное описание детали  Photometric Front Ends
PDF  66 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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ADPD107 датащи(HTML) 55 Page - Analog Devices

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Data Sheet
ADPD105/ADPD106/ADPD107
Rev. A | Page 55 of 66
Address
Data Bit
Default
Value
Access
Name
Description
0x3C
[15:14]
0x0
R/W
Reserved
Write 0x0.
[13:11]
0x6
R/W
Reserved
Write 0x6.
10
0x0
R/W
Reserved
Reserved.
9
0x0
R/W
V_CATHODE
0x0: 1.3 V (identical to anode voltage); recommended setting.
0x1: 1.8 V (reverse bias photodiode by 550 mV). This
setting may add noise.
[8:3]
0x00
R/W
AFE_POWERDOWN
AFE channels power-down select.
0x0: keeps all channels on.
Bit 3: power down Channel 1 TIA op amp.
Bit 4: power down Channel 1 BPF op amp.
Bit 5: power down Channel 1 integrator op amp.
Bit 6: power down Channel 2, Channel 3, and Channel 4
TIA op amp.
Bit 7: power down Channel 2, Channel 3, and Channel 4
BPF op amp.
Bit 8: power down Channel 2, Channel 3, and Channel 4
integrator op amp.
[2:0]
0x6
R/W
Reserved
Write 0x6.
0x54
15
0x0
R/W
SLOTB_SINGLE_CH_DIG_INT
0: in Time Slot B, use all four photodiode channels in
parallel for digital integration (default setting for highest
dynamic range).
1: in Time Slot B, use only Channel 1 for digital integration.
This limits connection to PD1 or PD5.
14
0x0
R/W
SLOTA_SINGLE_CH_DIG_INT
0: in Time Slot A, use all four photodiode channels in
parallel for digital integration (default setting for highest
dynamic range)
1: in Time Slot A, use only Channel 1 for digital integration.
This limits connection to PD1 or PD5.
[13:12]
0x0
R/W
SLEEP_V_CATHODE
If Bit 7 = 1; this setting is applied to the cathode voltage
while the device is in sleep mode. The anode voltage is
always set to the cathode voltage in sleep mode.
0x0: VDD (1.8 V).
0x1: 1.3 V.
0x2: 1.55 V.
0x3: 0.0 V.
[11:10]
0x0
R/W
SLOTB_V_CATHODE
If Bit 7 = 1; this setting is applied to the cathode voltage
while the device is in Time Slot B operation. The anode
voltage is always 1.3 V in Time Slot B mode.
0x0: VDD (1.8 V).
0x1: 1.3 V.
0x2: 1.55 V.
0x3: 0.0 V (this forward biases a diode at the input).
[9:8]
0x0
R/W
SLOTA_V_CATHODE
If Bit 7 = 1; this setting is applied to the cathode voltage
while the device is in Time Slot A operation. The anode
voltage is always 1.3 V in Time Slot A mode.
0x0: VDD (1.8 V).
0x1: 1.3 V.
0x2: 1.55 V.
0x3: 0.0 V (this forward biases a diode at the input).
7
0x0
R/W
REG54_VCAT_ENABLE
0: use the cathode voltage settings defined by Register 0x3C,
Bit 9.
1: override Register 0x3C, Bit 9 with cathode settings
defined by Register 0x54, Bits[13:8].
[6:0]
0x20
R/W
Reserved
Reserved.



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