LP8733 datasheet(28/86 Pages) TI

28 / 86 page

LP8733

SNVSBK2 – SEPTEMBER 2019

www.ti.com

Product Folder Links: LP8733

Submit Documentation Feedback

7.3.7 Device Reset Scenarios

There are two reset methods implemented on the LP8733xx:

•

Software reset with the SW_RESET bit in the RESET register.

•

Undervoltage lockout (UVLO) reset from the VANA supply.

An software reset occurs when 1 is written to the SW_RESET bit. The bit is automatically cleared after writing.

This event disables all the regulators immediately, drives the GPO or GPO2 signals low, resets all the register

bits to the default values, and loads the OTP bits (see Figure 22). The I2C interface is not reset during a software

reset.

If the VANA supply voltage falls below the UVLO threshold level, then all the regulators are disabled immediately,

the GPO or GPO2 signals are driven low, and all the register bits are reset to the default values. When the VANA

supply voltage transitions above the UVLO threshold level, an internal POR occurs. The OTP bits are loaded to

the registers and a startup is initiated according to the register settings.

7.3.8 Diagnosis and Protection Features

The LP8733xx is capable of providing four levels of protection features:

•

Information of valid regulator output voltage, which sets interrupt or PGOOD signal.

•

Warnings for diagnosis, which sets interrupt.

•

Protection events, which are disabling the regulators.

•

Faults, which are causing the device to shutdown.

The LP8733xx sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin

is pulled low. The nINT is released again after a clear of flags is complete. The nINT signal stays low until all the

pending interrupts are cleared.

When a fault is detected or software requested reset, it is indicated by a RESET_REG_INT interrupt flag in the

INT_TOP_2 register after next start-up. If the RESET_REG_MASK is set to masked in the OTP, then the

interrupt is not generated. The mask bit change with I2C does not affect, because the RESET_REG_MASK bit is

loaded from the OTP during reset sequence.

LP8733 датащи(PDF) 28 Page - Texas Instruments