LP8733 datasheet(23/86 Pages) TI

23 / 86 page

LP8733

www.ti.com

SNVSBK2 – SEPTEMBER 2019

Product Folder Links: LP8733

Submit Documentation Feedback

•

Using the BUCKx_EN bit in the BUCKx_CTRL_1 register (the BUCKx_EN_PIN_CTRL bit is 0 in the

BUCKx_CTRL_1 register).

•

Using the EN control pin (the BUCKx_EN bit and the BUCKx_EN_PIN_CTRL bit is 1).

Similarly, there are two ways to enable and disable the LDO regulators:

•

Using the LDOx_EN bit in the LDOx_CTRL register (the LDOx_EN_PIN_CTRL bit is 0 in the LDOx_CTRL

•

Using the EN control pin (the LDOx_EN bit is 1 and the LDOx_EN_PIN_CTRL bit is 1).

If the EN control pin is used for enable and disable, then the following occurs:

•

The delay from the control signal rising edge to start-up is set by the BUCKx_STARTUP_DELAY[3:0] bits in

the BUCKx_DELAY register and the LDOx_STARTUP_DELAY[3:0] bits in the LDOx_DELAY register.

•

The delay from the control signal falling edge to shutdown is set by the BUCKx_SHUTDOWN_DELAY[3:0]

bits in the BUCKx_DELAY register and the LDOx_SHUTDOWN_DELAY[3:0] bits in the LDOx_DELAY

The delays are only valid for the EN signal transitions and not for control with I2C writings to the BUCKx_EN and

the LDOx_EN bits.

The control of the regulator (with 0-ms delays) is shown in Table 3. Dual-phase regulator is controlled with

registers of the master phase.

Table 3. Regulator Control

BUCKx_EN AND

LDOx_EN

BUCKx_EN_PIN_CTRL

AND

LDOx_EN_PIN_CTRL

EN PIN

BUCKx OUTPUT VOLTAGE AND

LDOx OUTPUT VOLTAGE

Enable and disable control

with the BUCKx_EN and

the LDOx_EN bit

Don't Care

Disabled

Don't Care

BUCKx_VSET[7:0] and LDOx_VSET[4:0]

Enable and disable control

with the EN pin

Low

Disabled

High

BUCKx_VSET[7:0] and LDOx_VSET[4:0]

The buck regulator is enabled by the EN pin or by I2C writing, as shown in Figure 13. The soft-start circuit limits

the in-rush current during start-up. When the output voltage rises to a 0.35-V level, the output voltage becomes

slew-rate controlled. If there is a short circuit at the output, and the output voltage does not increase above the

0.35-V level in 1 ms or the output voltage drops below 0.35-V level during operation (for minimum of 1 ms), then

the regulator is disabled, and the BUCKx_SC_INT interrupt in the INT_BUCK register is set. When the output

voltage reaches the the Power-Good threshold level, the BUCKx_PG_INT interrupt flag in the INT_BUCK register

is set. The Power-Good interrupt flag, when reaching the valid output voltage, can be masked using the

BUCKx_PGR_MASK bit in the BUCK_MASK register. The Power-Good interrupt flag can also be generated

when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection is set by the

BUCKx_PGF_MASK bit in the BUCK_MASK register. A BUCKx_PG_STAT bit in the BUCK_STAT register

always shows the validity of the output voltage; 1 means valid and 0 means invalid output voltage. A

PGOOD_WINDOW_BUCK bit in the PGOOD_CTRL_1 register sets the detection method for the valid buck

output voltage, either under-voltage detection, or under-voltage and over-voltage detection.

LP8733 датащи(PDF) 23 Page - Texas Instruments

LP8733 датащи(HTML) 23 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

датащи скачать

ссылки URL