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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP8733 датащи(PDF) 22 Page - Texas Instruments |
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LP8733 датащи(HTML) 22 Page - Texas Instruments |
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22 / 86 page  24 MHz RC Oscillator CLKIN Divider ´(;7 _CLK _)5(4´ PLL Divider 24 CLKIN Detector Clock Select Logic Internal 24 MHz clock 1 MHz 1 MHz ´(1 _3//´ 24 MHz 22 LP8733 SNVSBK2 – SEPTEMBER 2019 www.ti.com Product Folder Links: LP8733 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Feature Description (continued) The SYNC_CLK_INT interrupt in the INT_TOP_1 register is also generated in cases where the external clock is expected but is not available. These cases occur when EN_PLL is 1 during start-up (read OTP-to-standby transition) and during Buck regulator enable (standby-to-active transition). Figure 12. Clock and PLL Module Table 2. PLL Operation DEVICE OPERATION MODE EN_PLL PLL AND CLOCK DETECTOR STATE INTERRUPT FOR EXTERNAL CLOCK CLOCK STANDBY 0 Disabled No Internal RC ACTIVE 0 Disabled No Internal RC STANDBY 1 Enabled When external clock appears or disappears Automatic change to external clock when available ACTIVE 1 Enabled When external clock appears or disappears Automatic change to external clock when available 7.3.3 Low-Dropout Linear Regulators (LDOs) The LP8733xx device includes two identical linear regulators, LDO0 and LDO1, which target analog loads with low noise requirements. The LDO regulators deliver 0.8-V to 3.3-V regulated voltage rails from a 2.5-V to 5.5-V input voltage. Both regulators have dedicated inputs which can be higher or lower than the device system voltage V(VANA) to minimize the power dissipation. 7.3.4 Power-Up The power-up sequence for the LP8733xx is as follows: • The VANA and VIN_Bx reach minimum recommended levels (VVANA > VANAUVLO). This initiates power-on- reset (POR), OTP reading, and enables the system I/O interface. The I2C host should allow at least 1.2 ms before writing or reading data to the LP8733xx. • The device enters standby mode. • The host can change the default register setting by I2C if needed. • The regulators can be enabled and disabled. • The GPO signals can be controlled by the EN pin and the I2C interface. Transitions between the operating modes are shown in Modes of Operation. 7.3.5 Regulator Control 7.3.5.1 Enabling and Disabling Regulators The regulators can be enabled when the device is in STANDBY or ACTIVE state. There are two ways to enable and disable the buck regulators: |
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