 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
LP8733 датащи(PDF) 59 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
LP8733 датащи(HTML) 59 Page - Texas Instruments |
|
|
59 / 86 page  59 LP8733 www.ti.com SNVSBK2 – SEPTEMBER 2019 Product Folder Links: LP8733 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Table 40. TOP_MASK_1 Register Field Descriptions (continued) Bits Field Type Default Description 2 TDIE_WARN _MASK R/W X Masking for the thermal warning interrupt (TDIE_WARN_INT in INT_TOP_1 register): 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect the TDIE_WARN_STAT status bit in the TOP_STAT register. 1 Reserved - do not use R/W 0 0 I_MEAS _MASK R/W X Masking for the load current measurement ready interrupt (MEAS_INT in INT_TOP_1 register): 0 - Interrupt is generated. 1 - Interrupt is not generated. 7.6.1.34 TOP_MASK_2 TOP_MASK_2 is shown in Table 41, Address: 0x21 Figure 62. TOP_MASK_2 Register D7 D6 D5 D4 D3 D2 D1 D0 Reserved - do not use RESET_REG _MASK Table 41. TOP_MASK_2 Register Field Descriptions Bits Field Type Default Description 7:1 Reserved - do not use R/W 000 0000 0 RESET_REG _MASK R/W X Masking for register reset interrupt (RESET_REG_INT in INT_TOP_2 register): 0 - Interrupt is generated. 1 - Interrupt is not generated. This change of this bit by I2C writing has no effect because it will be read from OTP memory during reset. 7.6.1.35 BUCK_MASK BUCK_MASK is shown in Table 42, Address: 0x22 Figure 63. BUCK_MASK Register D7 D6 D5 D4 D3 D2 D1 D0 BUCK1_PGF _MASK BUCK1_PGR _MASK Reserved - do not use BUCK1_ILIM _MASK BUCK0_PGF _MASK BUCK0_PGR _MASK Reserved - do not use BUCK0_ILIM _MASK Table 42. BUCK_MASK Register Field Descriptions Bits Field Type Default Description 7 BUCK1_PGF_MAS K R/W X Masking of the Power Good invalid detection for the Buck1 power good interrupt (BUCK1_PG_INT in INT_BUCK register): 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect the BUCK1_PG_STAT status bit in the BUCK_STAT register. 6 BUCK1_PGR_MAS K R/W X Masking of the Power Good valid detection for the Buck1 Power Good interrupt (BUCK1_PG_INT in INT_BUCK register): 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect the BUCK1_PG_STAT status bit in the BUCK_STAT register. 5 Reserved - do not use R 0 4 BUCK1_ILIM _MASK R/W X Masking for the Buck1 current limit detection interrupt (BUCK1_ILIM_INT in INT_BUCK register): 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect the BUCK1_ILIM_STAT status bit in the BUCK_STAT register. |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
