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LP8733 датащи(PDF) 51 Page - Texas Instruments |
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LP8733 датащи(HTML) 51 Page - Texas Instruments |
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51 / 86 page ![]() 51 LP8733 www.ti.com SNVSBK2 – SEPTEMBER 2019 Product Folder Links: LP8733 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Table 25. GPO2_DELAY Register Field Descriptions (continued) Bits Field Type Default Description 3:0 GPO2_ STARTUP_ DELAY[3:0] R/W X Delay for the GPO2 rising edge from the EN signal's rising edge: 0x0 - 0 ms 0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.) ... 0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in the CONFIG register.) 7.6.1.19 GPO_CTRL GPO_CTRL is shown in Table 26, Address: 0x12 Figure 47. GPO_CTRL Register D7 D6 D5 D4 D3 D2 D1 D0 Reserved - do not use GPO2_OD GPO2_EN_PIN _CTRL GPO2_EN Reserved - do not use GPO_OD GPO_EN_PIN_ CTRL GPO_EN Table 26. GPO_CTRL Register Field Descriptions Bits Field Type Default Description 7 Reserved - do not use R 0 6 GP02_OD R/W X GPO2 signal type when configured as the General Purpose Output (CLKIN pin): 0 - Push-pull output (VANA level) 1 - Open-drain output 5 GPO2_EN_PIN_C TRL R/W X Control for the GPO2: 0 - Only the GPO2_EN bit controls the GPO2 1 - GPO2_EN bit and the EN pin control the GPO2. 4 GPO2_EN R/W X Output level of the GPO2 signal (when configured as the General Purpose Output): 0 - Logic low level 1 - Logic high level 3 Reserved - do not use R 0 2 GPO_OD R/W X GPO signal type: 0 - Push-pull output (VANA level) 1 - Open-drain output 1 GPO_EN_PIN_CT RL R/W X Control for the GPO: 0 - Only the GPO_EN bit controls the GPO 1 - GPO_EN bit and the EN pin control the GPO. 0 GPO_EN R/W X Output level of the GPO signal: 0 - Logic low level 1 - Logic high level 7.6.1.20 CONFIG CONFIG is shown in Table 27, Address: 0x13 Figure 48. CONFIG Register D7 D6 D5 D4 D3 D2 D1 D0 Reserved - do not use STARTUP_DE LAY_SEL SHUTDOWN_ DELAY_SEL CLKIN_PIN_SE L CLKIN_PD EN2_PD TDIE_WARN_ LEVEL EN_SPREAD _SPEC Table 27. CONFIG Register Field Descriptions Bits Field Type Default Description 7 Reserved - do not use R/W 0 6 STARTUP_DELAY _SEL R/W X Startup delay range from the EN signals. 0 - 0 ms - 7.5 ms with 0.5 ms steps 1 - 0 ms - 15 ms with 1 ms steps |
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